tec: init freq pins for 1 MHz switching

tec: fix wrong SHDN pins
tec: setup iset_width
2019-11-14 01:59:57 +01:00 · 2019-11-13 20:13:57 +01:00 · 2019-11-13 20:12:25 +01:00 · 2019-11-13 20:01:17 +01:00 · 2019-11-13 19:50:14 +01:00 · 2019-11-13 19:23:49 +01:00
32 changed files with 19012 additions and 37 deletions
--- a/.gitignore
+++ b/.gitignore
@ -0,0 +1,2 @@
+firmware/target/
+**/*.rs.bk
--- a/README.md
+++ b/README.md
@ -1,37 +0,0 @@
-Ionpak
-======
-
-A modern, low-cost universal controller for ionization vacuum gauges.
-
-![Prototype picture](https://raw.githubusercontent.com/m-labs/ionpak/master/proto_rev1_resized.jpg)
-
-Flyback transformer construction
--------------------------------
-
-TR300
-*****
-
-Use EPCOS coilformer B66208X1010T1. Wind 5 turns on the primary and spread them across the length of the coilformer - it is important that the air gap between the cores is covered by windings. Wind 70 turns on the secondary in multiple layers. As with all flyback transformers, the polarity of the windings is critical. Assemble with EPCOS cores B66317G500X127 and B66317GX127 (one half gapped core, one half ungapped core), and corresponding clips.
-
-TR350
-*****
-
-Use EPCOS coilformer B66206W1110T1 and cores B66311G250X127 and B66311GX127. Both the primary and the secondary have 5 turns and must be wound together, interleaving the windings. The same remarks as for TR300 apply.
-
-Errata
------
-
-PCB rev 1
-*********
-
-* R307 needs more clearance from D400
-* Pins 1 and 12 of U502 need pull-downs
-* Pin 1 of U501 needs pull-up
-* D203 reversed polarity
-* R236 and R234 are swapped
-* Q301 needs to be NPN, change to BC817
-* increase R307 -> 3.3Kohm and increase R300 -> 33Kohm
-* C201: oscillates at 0 and 1nF, stable at 100nF
-* add clamp diodes to GND on op-amp outputs to ADC when op-amp has negative supply
-* R214 -> 4.7k
-* LM339PT is in TSSOP package. Change for SOIC P/N
--- a/channel-rust-nightly.toml
+++ b/channel-rust-nightly.toml
--- a/default.nix
+++ b/default.nix
@ -0,0 +1,62 @@
+{ # Use master branch of the overlay by default
+  mozillaOverlay ? import (builtins.fetchTarball https://github.com/mozilla/nixpkgs-mozilla/archive/master.tar.gz),
+  rustManifest ? ./channel-rust-nightly.toml,
+}:
+
+let
+  pkgs = import <nixpkgs> { overlays = [ mozillaOverlay ]; };
+in
+with pkgs;
+let
+  rustcSrc = pkgs.fetchgit {
+    url = https://github.com/rust-lang/rust.git;
+    # master of 2019-11-09
+    rev = "ac162c6abe34cdf965afc0389f6cefa79653c63b";
+    sha256 = "06c5gws1mrpr69z1gzs358zf7hcsg6ky8n4ha0vv2s9d9w93x1kj";
+    fetchSubmodules = true;
+  };
+  target = "thumbv7em-none-eabihf";
+  targets = [ target ];
+  rustChannelOfTargets = _channel: _date: targets:
+    (pkgs.lib.rustLib.fromManifestFile rustManifest {
+      inherit (pkgs) stdenv fetchurl patchelf;
+    }).rust.override { inherit targets; };
+  rust =
+    rustChannelOfTargets "nightly" null targets;
+  rustPlatform = recurseIntoAttrs (makeRustPlatform {
+    rustc = rust // { src = rustcSrc; };
+    cargo = rust;
+  });
+  gcc = pkgsCross.armv7l-hf-multiplatform.buildPackages.gcc;
+  xbuildRustPackage = attrs:
+    let
+      buildPkg = rustPlatform.buildRustPackage attrs;
+    in
+    buildPkg.overrideAttrs ({ name, nativeBuildInputs, ... }: {
+      nativeBuildInputs =
+        nativeBuildInputs ++ [ cargo-xbuild ];
+      buildPhase = ''
+        cargo xbuild --release --frozen
+      '';
+      XARGO_RUST_SRC = "${rustcSrc}/src";
+      installPhase = ''
+        mkdir $out
+        cp target/${target}/release/${name} $out/${name}.elf
+      '';
+    });
+  firmware = xbuildRustPackage {
+    name = "firmware";
+    src = ./firmware;
+    cargoSha256 = "0lf8h5g8sas36cxzqy0p65qqivnihh4gn4mkc1k210xp7niaymc5";
+    nativeBuildInputs = [
+      gcc
+    ];
+    "CC_${target}" = "${gcc}/bin/armv7l-unknown-linux-gnueabihf-gcc";
+    RUST_COMPILER_RT_ROOT = "${rustcSrc}/src/llvm-project/compiler-rt";
+    checkPhase = ''
+      cargo test --target=${hostPlatform.config}
+    '';
+  };
+in {
+  inherit pkgs rustPlatform rustcSrc gcc firmware;
+}
--- a/firmware/.cargo/config
+++ b/firmware/.cargo/config
@ -0,0 +1,8 @@
+[target.thumbv7em-none-eabihf]
+runner = "arm-none-eabi-gdb"
+rustflags = [
+  "-C", "link-arg=-Tlink.x",
+]
+
+[build]
+target = "thumbv7em-none-eabihf"
--- a/firmware/Cargo.lock
+++ b/firmware/Cargo.lock
@ -0,0 +1,421 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
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+
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+name = "bare-metal"
+version = "0.2.5"
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+dependencies = [
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+
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+
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+"checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
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--- a/firmware/Cargo.toml
+++ b/firmware/Cargo.toml
@ -0,0 +1,38 @@
+[package]
+name = "firmware"
+version = "1.0.0"
+authors = ["whitequark <whitequark@whitequark.org>"]
+edition = "2018"
+
+[build-dependencies]
+walkdir = "~2"
+
+[dependencies]
+libm = "0.1.4"
+cortex-m = { version = "0.6", features = ["const-fn"] }
+cortex-m-rt = "0.6"
+crc = { version = "~1", default-features = false }
+tm4c129x = { version = "0.9", features = ["rt"] }
+embedded-hal = { version = "0.2", features = ["unproven"] }
+nb = "0.1"
+cortex-m-semihosting = "0.3"
+byteorder = { version = "1.3", default-features = false }
+bit_field = "0.10"
+bare-metal = "0.2"
+lexical-core = { version = "~0.6", default-features = false }
+nom = { version = "~5", default-features = false }
+
+[dependencies.smoltcp]
+git = "https://github.com/m-labs/smoltcp.git"
+rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
+features = ["ethernet", "proto-ipv4", "socket-tcp"]
+default-features = false
+
+[dependencies.compiler_builtins]
+version = "0.1"
+default-features = false
+features = ["mem", "no-lang-items", "c"]
+
+[profile.release]
+lto = true
+debug = true
--- a/firmware/README.md
+++ b/firmware/README.md
@ -0,0 +1,75 @@
+# Thermostat v1 prototype firmware
+
+## Building
+
+### On Debian-based systems
+
+- install [rustup](https://rustup.rs/)
+
+```shell
+apt install gcc gcc-arm-none-eabi git-core
+rustup toolchain install nightly
+rustup update
+rustup target add thumbv7em-none-eabihf --toolchain nightly
+rustup default nightly
+rustup component add rust-src
+cargo install cargo-xbuild
+git clone https://github.com/llvm/llvm-project.git
+export RUST_COMPILER_RT_ROOT=`pwd`/llvm-project/compiler-rt
+
+cd firmware && cargo xbuild --release
+```
+
+The built ELF file will be at `target/thumbv7em-none-eabihf/release/ionpak-firmware`
+
+### Development build on NixOS
+
+Requires NixOS 19.09 or later for cargo-xbuild.
+
+```shell
+nix-shell --run "cd firmware && cargo xbuild --release"
+```
+
+## Network
+
+### Setup
+
+Ethernet, IP: 192.168.1.26/24
+
+Use telnet or netcat to connect to port 23/tcp (telnet)
+
+### Reading ADC input
+
+Set report mode to `once` to obtain the single next value. Report mode
+will turn itself off after the next reading.
+
+Set report mode to `continuous` for a continuous stream of input data.
+
+The scope of this setting is per TCP session.
+
+
+### Commands
+
+| Syntax                                | Function                                                   |
+| ---                                   | ---                                                        |
+| `report`                              | Show current input                                         |
+| `report mode`                         | Show current report mode                                   |
+| `report mode <off/on>`                | Set report mode                                            |
+| `pwm <0/1> max_i_pos <width> <total>` | Set PWM duty cycle for **max_i_pos** to *width / total*    |
+| `pwm <0/1> max_i_neg <width> <total>` | Set PWM duty cycle for **max_i_neg** to *width / total*    |
+| `pwm <0/1> max_v <width> <total>`     | Set PWM duty cycle for **max_v** to *width / total*        |
+| `pwm <0/1> <width> <total>`           | Set PWM duty cycle for **i_set** to manual *width / total* |
+| `pwm <0/1> pid`                       | Set PWM to be controlled by PID                            |
+| `pid`                                 | Show PID configuration                                     |
+| `pid <0/1> target <value>`            | Set the PID controller target                              |
+| `pid <0/1> kp <value>`                | Set proportional gain                                      |
+| `pid <0/1> ki <value>`                | Set integral gain                                          |
+| `pid <0/1> kd <value>`                | Set differential gain                                      |
+| `pid <0/1> output_min <value>`        | Set mininum output                                         |
+| `pid <0/1> output_max <value>`        | Set maximum output                                         |
+| `pid <0/1> integral_min <value>`      | Set integral lower bound                                   |
+| `pid <0/1> integral_max <value>`      | Set integral upper bound                                   |
+| `s-h`                                 | Show Steinhart-Hart equation parameters                    |
+| `s-h <0/1> <a/b/c> <value>`           | Set Steinhart-Hart parameter for a channel                 |
+| `s-h <0/1> parallel_r <value>`        | Set parallel resistance of the ADC                         |
+| `postfilter <0/1> rate <rate>`        | Set postfilter output data rate                            |
--- a/firmware/build.rs
+++ b/firmware/build.rs
@ -0,0 +1,22 @@
+extern crate walkdir;
+
+use std::env;
+use std::io::Write;
+use std::fs::File;
+use std::path::PathBuf;
+
+fn linker_script() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    println!("cargo:rerun-if-changed=memory.x");
+}
+
+fn main() {
+    linker_script();
+}
--- a/firmware/memory.x
+++ b/firmware/memory.x
@ -0,0 +1,7 @@
+MEMORY
+{
+  FLASH : ORIGIN = 0x00000000, LENGTH = 512K
+  RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);
--- a/firmware/openocd.cfg
+++ b/firmware/openocd.cfg
@ -0,0 +1,9 @@
+source [find interface/stlink-v2.cfg]
+transport select hla_swd
+set CHIPNAME tm4c1294kcpd
+set CPUTAPID 0x2ba01477
+source [find target/stellaris.cfg]
+
+program target/thumbv7em-none-eabihf/release/ionpak-firmware verify
+reset
+exit
--- a/firmware/src/ad7172/adc.rs
+++ b/firmware/src/ad7172/adc.rs
@ -0,0 +1,201 @@
+use embedded_hal::digital::v2::OutputPin;
+use embedded_hal::blocking::spi::Transfer;
+use super::checksum::{ChecksumMode, Checksum};
+use super::AdcError;
+use super::{
+    regs, regs::RegisterData,
+    Input, RefSource, PostFilter, DigitalFilterOrder,
+};
+
+/// AD7172-2 implementation
+///
+/// [Manual](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf)
+pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
+    spi: SPI,
+    nss: NSS,
+    checksum_mode: ChecksumMode,
+}
+
+impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
+    pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
+        let _ = nss.set_high();
+        let mut adc = Adc {
+            spi, nss,
+            checksum_mode: ChecksumMode::Off,
+        };
+        adc.reset()?;
+
+        Ok(adc)
+    }
+
+    /// `0x00DX` for AD7172-2
+    pub fn identify(&mut self) -> Result<u16, AdcError<SPI::Error>> {
+        self.read_reg(&regs::Id)
+            .map(|id| id.id())
+    }
+
+    pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), AdcError<SPI::Error>> {
+        // Cannot use update_reg() here because checksum_mode is
+        // updated between read_reg() and write_reg().
+        let mut ifmode = self.read_reg(&regs::IfMode)?;
+        ifmode.set_crc(mode);
+        self.checksum_mode = mode;
+        self.write_reg(&regs::IfMode, &mut ifmode)?;
+        Ok(())
+    }
+
+    pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), AdcError<SPI::Error>> {
+        self.update_reg(&regs::GpioCon, |data| {
+            data.set_sync_en(enable);
+        })
+    }
+
+    pub fn setup_channel(
+        &mut self, index: u8, in_pos: Input, in_neg: Input
+    ) -> Result<(), AdcError<SPI::Error>> {
+        self.update_reg(&regs::SetupCon { index }, |data| {
+            data.set_bipolar(false);
+            data.set_refbuf_pos(true);
+            data.set_refbuf_neg(true);
+            data.set_ainbuf_pos(true);
+            data.set_ainbuf_neg(true);
+            data.set_ref_sel(RefSource::External);
+        })?;
+        self.update_reg(&regs::FiltCon { index }, |data| {
+            data.set_enh_filt_en(true);
+            data.set_enh_filt(PostFilter::F16SPS);
+            data.set_order(DigitalFilterOrder::Sinc5Sinc1);
+        })?;
+        // let mut offset = <regs::Offset as regs::Register>::Data::empty();
+        // offset.set_offset(0);
+        // self.write_reg(&regs::Offset { index }, &mut offset);
+        self.update_reg(&regs::Channel { index }, |data| {
+            data.set_setup(index);
+            data.set_enabled(true);
+            data.set_a_in_pos(in_pos);
+            data.set_a_in_neg(in_neg);
+        })?;
+        Ok(())
+    }
+
+    pub fn get_postfilter(&mut self, index: u8) -> Result<Option<PostFilter>, AdcError<SPI::Error>> {
+        self.read_reg(&regs::FiltCon { index })
+            .map(|data| {
+                if data.enh_filt_en() {
+                    Some(data.enh_filt())
+                } else {
+                    None
+                }
+            })
+    }
+
+    pub fn set_postfilter(&mut self, index: u8, filter: Option<PostFilter>) -> Result<(), AdcError<SPI::Error>> {
+        self.update_reg(&regs::FiltCon { index }, |data| {
+            match filter {
+                None => data.set_enh_filt_en(false),
+                Some(filter) => {
+                    data.set_enh_filt_en(true);
+                    data.set_enh_filt(filter);
+                }
+            }
+        })
+    }
+
+    /// Returns the channel the data is from
+    pub fn data_ready(&mut self) -> Result<Option<u8>, AdcError<SPI::Error>> {
+        self.read_reg(&regs::Status)
+            .map(|status| {
+                if status.ready() {
+                    Some(status.channel())
+                } else {
+                    None
+                }
+            })
+    }
+
+    /// Get data
+    pub fn read_data(&mut self) -> Result<i32, AdcError<SPI::Error>> {
+        self.read_reg(&regs::Data)
+            .map(|data| data.data())
+    }
+
+    fn read_reg<R: regs::Register>(&mut self, reg: &R) -> Result<R::Data, AdcError<SPI::Error>> {
+        let mut reg_data = R::Data::empty();
+        let address = 0x40 | reg.address();
+        let mut checksum = Checksum::new(self.checksum_mode);
+        checksum.feed(address);
+        let checksum_out = checksum.result();
+        let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
+        for &mut b in reg_data.as_mut() {
+            checksum.feed(b);
+        }
+        let checksum_expected = checksum.result();
+        if checksum_expected != checksum_in {
+            return Err(AdcError::ChecksumMismatch(checksum_expected, checksum_in));
+        }
+        Ok(reg_data)
+    }
+
+    fn write_reg<R: regs::Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), AdcError<SPI::Error>> {
+        let address = reg.address();
+        let mut checksum = Checksum::new(match self.checksum_mode {
+            ChecksumMode::Off => ChecksumMode::Off,
+            // write checksums are always crc
+            ChecksumMode::Xor => ChecksumMode::Crc,
+            ChecksumMode::Crc => ChecksumMode::Crc,
+        });
+        checksum.feed(address);
+        for &mut b in reg_data.as_mut() {
+            checksum.feed(b);
+        }
+        let checksum_out = checksum.result();
+        self.transfer(address, reg_data.as_mut(), checksum_out)?;
+        Ok(())
+    }
+
+    fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, AdcError<SPI::Error>>
+    where
+        R: regs::Register,
+        F: FnOnce(&mut R::Data) -> A,
+    {
+        let mut reg_data = self.read_reg(reg)?;
+        let result = f(&mut reg_data);
+        self.write_reg(reg, &mut reg_data)?;
+        Ok(result)
+    }
+
+    pub fn reset(&mut self) -> Result<(), SPI::Error> {
+        let mut buf = [0xFFu8; 8];
+        let _ = self.nss.set_low();
+        let result = self.spi.transfer(&mut buf);
+        let _ = self.nss.set_high();
+        result?;
+        Ok(())
+    }
+
+    fn transfer<'w>(&mut self, addr: u8, reg_data: &'w mut [u8], checksum: Option<u8>) -> Result<Option<u8>, SPI::Error> {
+        let mut addr_buf = [addr];
+
+        let _ = self.nss.set_low();
+        let result = match self.spi.transfer(&mut addr_buf) {
+            Ok(_) => self.spi.transfer(reg_data),
+            Err(e) => Err(e),
+        };
+        let result = match (result, checksum) {
+            (Ok(_),None) =>
+                Ok(None),
+            (Ok(_), Some(checksum_out)) => {
+                let mut checksum_buf = [checksum_out; 1];
+                match self.spi.transfer(&mut checksum_buf) {
+                    Ok(_) => Ok(Some(checksum_buf[0])),
+                    Err(e) => Err(e),
+                }
+            }
+            (Err(e), _) =>
+                Err(e),
+        };
+        let _ = self.nss.set_high();
+
+        result
+    }
+}
--- a/firmware/src/ad7172/checksum.rs
+++ b/firmware/src/ad7172/checksum.rs
@ -0,0 +1,54 @@
+#[derive(Clone, Copy, PartialEq)]
+#[repr(u8)]
+pub enum ChecksumMode {
+    Off = 0b00,
+    /// Seems much less reliable than `Crc`
+    Xor = 0b01,
+    Crc = 0b10,
+}
+
+impl From<u8> for ChecksumMode {
+    fn from(x: u8) -> Self {
+        match x {
+            0 => ChecksumMode::Off,
+            1 => ChecksumMode::Xor,
+            _ => ChecksumMode::Crc,
+        }
+    }
+}
+
+pub struct Checksum {
+    mode: ChecksumMode,
+    state: u8,
+}
+
+impl Checksum {
+    pub fn new(mode: ChecksumMode) -> Self {
+        Checksum { mode, state: 0 }
+    }
+
+    pub fn feed(&mut self, input: u8) {
+        match self.mode {
+            ChecksumMode::Off => {},
+            ChecksumMode::Xor => self.state ^= input,
+            ChecksumMode::Crc => {
+                for i in 0..8 {
+                    let input_mask = 0x80 >> i;
+                    self.state = (self.state << 1) ^
+                        if ((self.state & 0x80) != 0) != ((input & input_mask) != 0) {
+                            0x07 /* x8 + x2 + x + 1 */
+                        } else {
+                            0
+                        };
+                }
+            }
+        }
+    }
+
+    pub fn result(&self) -> Option<u8> {
+        match self.mode {
+            ChecksumMode::Off => None,
+            _ => Some(self.state)
+        }
+    }
+}
--- a/firmware/src/ad7172/mod.rs
+++ b/firmware/src/ad7172/mod.rs
@ -0,0 +1,198 @@
+use core::fmt;
+
+pub mod regs;
+mod checksum;
+pub use checksum::ChecksumMode;
+mod adc;
+pub use adc::*;
+
+#[derive(Clone, Debug, PartialEq)]
+pub enum AdcError<SPI> {
+    SPI(SPI),
+    ChecksumMismatch(Option<u8>, Option<u8>),
+}
+
+impl<SPI> From<SPI> for AdcError<SPI> {
+    fn from(e: SPI) -> Self {
+        AdcError::SPI(e)
+    }
+}
+
+#[derive(Clone, Copy, Debug)]
+#[repr(u8)]
+pub enum Input {
+    Ain0 = 0,
+    Ain1 = 1,
+    Ain2 = 2,
+    Ain3 = 3,
+    Ain4 = 4,
+    TemperaturePos = 17,
+    TemperatureNeg = 18,
+    AnalogSupplyPos = 19,
+    AnalogSupplyNeg = 20,
+    RefPos = 21,
+    RefNeg = 22,
+    Invalid = 0b11111,
+}
+
+impl From<u8> for Input {
+    fn from(x: u8) -> Self {
+        match x {
+            0 => Input::Ain0,
+            1 => Input::Ain1,
+            2 => Input::Ain2,
+            3 => Input::Ain3,
+            4 => Input::Ain4,
+            17 => Input::TemperaturePos,
+            18 => Input::TemperatureNeg,
+            19 => Input::AnalogSupplyPos,
+            20 => Input::AnalogSupplyNeg,
+            21 => Input::RefPos,
+            22 => Input::RefNeg,
+            _ => Input::Invalid,
+        }
+    }
+}
+
+impl fmt::Display for Input {
+    fn fmt(&self, fmt: &mut fmt::Formatter) -> Result<(), fmt::Error> {
+        use Input::*;
+
+        match self {
+            Ain0 => "ain0",
+            Ain1 => "ain1",
+            Ain2 => "ain2",
+            Ain3 => "ain3",
+            Ain4 => "ain4",
+            TemperaturePos => "temperature+",
+            TemperatureNeg => "temperature-",
+            AnalogSupplyPos => "analogsupply+",
+            AnalogSupplyNeg => "analogsupply-",
+            RefPos => "ref+",
+            RefNeg => "ref-",
+            _ => "<INVALID>",
+        }.fmt(fmt)
+    }
+}
+
+/// Reference source for ADC conversion
+#[repr(u8)]
+pub enum RefSource {
+    /// External reference
+    External = 0b00,
+    /// Internal 2.5V reference
+    Internal = 0b10,
+    /// AVDD1 − AVSS
+    Avdd1MinusAvss = 0b11,
+    Invalid = 0b01,
+}
+
+impl From<u8> for RefSource {
+    fn from(x: u8) -> Self {
+        match x {
+            0 => RefSource::External,
+            1 => RefSource::Internal,
+            2 => RefSource::Avdd1MinusAvss,
+            _ => RefSource::Invalid,
+        }
+    }
+}
+
+impl fmt::Display for RefSource {
+    fn fmt(&self, fmt: &mut fmt::Formatter) -> Result<(), fmt::Error> {
+        use RefSource::*;
+
+        match self {
+            External => "external",
+            Internal => "internal",
+            Avdd1MinusAvss => "avdd1-avss",
+            _ => "<INVALID>",
+        }.fmt(fmt)
+    }
+}
+
+#[derive(Clone, Copy)]
+#[repr(u8)]
+pub enum PostFilter {
+    /// 27 SPS, 47 dB rejection, 36.7 ms settling
+    F27SPS = 0b010,
+    /// 21.25 SPS, 62 dB rejection, 40 ms settling
+    F21SPS = 0b011,
+    /// 20 SPS, 86 dB rejection, 50 ms settling
+    F20SPS = 0b101,
+    /// 16.67 SPS, 92 dB rejection, 60 ms settling
+    F16SPS = 0b110,
+    Invalid = 0b111,
+}
+
+impl PostFilter {
+    pub const VALID_VALUES: &'static [Self] = &[
+        PostFilter::F27SPS,
+        PostFilter::F21SPS,
+        PostFilter::F20SPS,
+        PostFilter::F16SPS,
+    ];
+
+    pub fn closest(rate: f32) -> Option<Self> {
+        /// (x - y).abs()
+        fn d(x: f32, y: f32) -> f32 {
+            if x >= y {
+                x - y
+            } else {
+                y - x
+            }
+        }
+
+        let mut best: Option<(f32, Self)> = None;
+        for value in Self::VALID_VALUES {
+            let error = d(rate, value.output_rate().unwrap());
+            let better = best
+                .map(|(best_error, _)| error < best_error)
+                .unwrap_or(true);
+            if better {
+                best = Some((error, *value));
+            }
+        }
+        best.map(|(_, best)| best)
+    }
+
+    /// Samples per Second
+    pub fn output_rate(&self) -> Option<f32> {
+        match self {
+            PostFilter::F27SPS => Some(27.0),
+            PostFilter::F21SPS => Some(21.25),
+            PostFilter::F20SPS => Some(20.0),
+            PostFilter::F16SPS => Some(16.67),
+            PostFilter::Invalid => None,
+        }
+    }
+}
+
+impl From<u8> for PostFilter {
+    fn from(x: u8) -> Self {
+        match x {
+            0b010 => PostFilter::F27SPS,
+            0b011 => PostFilter::F21SPS,
+            0b101 => PostFilter::F20SPS,
+            0b110 => PostFilter::F16SPS,
+            _ => PostFilter::Invalid,
+        }
+    }
+}
+
+#[repr(u8)]
+pub enum DigitalFilterOrder {
+    Sinc5Sinc1 = 0b00,
+    Sinc3 = 0b11,
+    Invalid = 0b10,
+}
+
+impl From<u8> for DigitalFilterOrder {
+    fn from(x: u8) -> Self {
+        match x {
+            0b00 => DigitalFilterOrder::Sinc5Sinc1,
+            0b11 => DigitalFilterOrder::Sinc3,
+            _ => DigitalFilterOrder::Invalid,
+        }
+    }
+}
--- a/firmware/src/ad7172/regs.rs
+++ b/firmware/src/ad7172/regs.rs
@ -0,0 +1,260 @@
+use byteorder::{BigEndian, ByteOrder};
+use bit_field::BitField;
+
+use super::*;
+
+pub trait Register {
+    type Data: RegisterData;
+    fn address(&self) -> u8;
+}
+pub trait RegisterData {
+    fn empty() -> Self;
+    fn as_mut(&mut self) -> &mut [u8];
+}
+
+macro_rules! def_reg {
+    ($Reg: ident, $reg: ident, $addr: expr, $size: expr) => {
+        /// AD7172 register
+        pub struct $Reg;
+        impl Register for $Reg {
+            /// Register contents
+            type Data = $reg::Data;
+            /// Register address
+            fn address(&self) -> u8 {
+                $addr
+            }
+        }
+        mod $reg {
+            /// Register contents
+            pub struct Data(pub [u8; $size]);
+            impl super::RegisterData for Data {
+                /// Generate zeroed register contents
+                fn empty() -> Self {
+                    Data([0; $size])
+                }
+                /// Borrow for SPI transfer
+                fn as_mut(&mut self) -> &mut [u8] {
+                    &mut self.0
+                }
+            }
+        }
+    };
+    ($Reg: ident, u8, $reg: ident, $addr: expr, $size: expr) => {
+        pub struct $Reg { pub index: u8, }
+        impl Register for $Reg {
+            type Data = $reg::Data;
+            fn address(&self) -> u8 {
+                $addr + self.index
+            }
+        }
+        mod $reg {
+            pub struct Data(pub [u8; $size]);
+            impl super::RegisterData for Data {
+                fn empty() -> Self {
+                    Data([0; $size])
+                }
+                fn as_mut(&mut self) -> &mut [u8] {
+                    &mut self.0
+                }
+            }
+        }
+    }
+}
+
+macro_rules! reg_bit {
+    ($getter: ident, $byte: expr, $bit: expr, $doc: expr) => {
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $getter(&self) -> bool {
+            self.0[$byte].get_bit($bit)
+        }
+    };
+    ($getter: ident, $setter: ident, $byte: expr, $bit: expr, $doc: expr) => {
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $getter(&self) -> bool {
+            self.0[$byte].get_bit($bit)
+        }
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $setter(&mut self, value: bool) {
+            self.0[$byte].set_bit($bit, value);
+        }
+    };
+}
+
+macro_rules! reg_bits {
+    ($getter: ident, $byte: expr, $bits: expr, $doc: expr) => {
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $getter(&self) -> u8 {
+            self.0[$byte].get_bits($bits)
+        }
+    };
+    ($getter: ident, $setter: ident, $byte: expr, $bits: expr, $doc: expr) => {
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $getter(&self) -> u8 {
+            self.0[$byte].get_bits($bits)
+        }
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $setter(&mut self, value: u8) {
+            self.0[$byte].set_bits($bits, value);
+        }
+    };
+    ($getter: ident, $byte: expr, $bits: expr, $ty: ty, $doc: expr) => {
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $getter(&self) -> $ty {
+            self.0[$byte].get_bits($bits) as $ty
+        }
+    };
+    ($getter: ident, $setter: ident, $byte: expr, $bits: expr, $ty: ty, $doc: expr) => {
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $getter(&self) -> $ty {
+            self.0[$byte].get_bits($bits).into()
+        }
+        #[allow(unused)]
+        #[doc = $doc]
+        pub fn $setter(&mut self, value: $ty) {
+            self.0[$byte].set_bits($bits, value as u8);
+        }
+    };
+}
+
+def_reg!(Status, status, 0x00, 1);
+impl status::Data {
+    /// Is there new data to read?
+    pub fn ready(&self) -> bool {
+        ! self.not_ready()
+    }
+
+    reg_bit!(not_ready, 0, 7, "No data ready indicator");
+    reg_bits!(channel, 0, 0..=1, "Channel for which data is ready");
+    reg_bit!(adc_error, 0, 6, "ADC error");
+    reg_bit!(crc_error, 0, 5, "SPI CRC error");
+    reg_bit!(reg_error, 0,4, "Register error");
+}
+
+def_reg!(IfMode, if_mode, 0x02, 2);
+impl if_mode::Data {
+    reg_bits!(crc, set_crc, 1, 2..=3, ChecksumMode, "SPI checksum mode");
+}
+
+def_reg!(Data, data, 0x04, 3);
+impl data::Data {
+    pub fn data(&self) -> i32 {
+        let raw =
+            (u32::from(self.0[0]) << 16) |
+            (u32::from(self.0[1]) << 8) |
+            u32::from(self.0[2]);
+        if raw & 0x80_0000 != 0 {
+            ((raw & 0x7F_FFFF) | 0x8000_0000) as i32
+        } else {
+            raw as i32
+        }
+    }
+}
+
+def_reg!(GpioCon, gpio_con, 0x06, 2);
+impl gpio_con::Data {
+    reg_bit!(sync_en, set_sync_en, 0, 3, "Enables the SYNC/ERROR pin as a sync input");
+}
+
+def_reg!(Id, id, 0x07, 2);
+impl id::Data {
+    pub fn id(&self) -> u16 {
+        BigEndian::read_u16(&self.0)
+    }
+}
+
+def_reg!(Channel, u8, channel, 0x10, 2);
+impl channel::Data {
+    reg_bit!(enabled, set_enabled, 0, 7, "Channel enabled");
+    reg_bits!(setup, set_setup, 0, 4..=5, "Setup number");
+
+    /// Which input is connected to positive input of this channel
+    #[allow(unused)]
+    pub fn a_in_pos(&self) -> Input {
+        ((self.0[0].get_bits(0..=1) << 3) |
+         self.0[1].get_bits(5..=7)).into()
+    }
+    /// Set which input is connected to positive input of this channel
+    #[allow(unused)]
+    pub fn set_a_in_pos(&mut self, value: Input) {
+        let value = value as u8;
+        self.0[0].set_bits(0..=1, value >> 3);
+        self.0[1].set_bits(5..=7, value & 0x7);
+    }
+    reg_bits!(a_in_neg, set_a_in_neg, 1, 0..=4, Input,
+              "Which input is connected to negative input of this channel");
+
+    // const PROPS: &'static [Property<Self>] = &[
+    //     Property::named("enable")
+    //         .readable(&|self_: &Self| self_.enabled().into())
+    //         .writebale(&|self_: &mut Self, value| self_.set_enabled(value != 0)),
+    //     Property::named("setup")
+    //         .readable(&|self_: &Self| self_.0[0].get_bits(4..=5).into())
+    //         .writeable(&|self_: &mut Self, value| {
+    //             self_.0[0].set_bits(4..=5, value as u8);
+    //         }),
+    // ];
+
+    // pub fn props() -> &'static [Property<Self>] {
+    //     Self::PROPS
+    // }
+}
+
+def_reg!(SetupCon, u8, setup_con, 0x20, 2);
+impl setup_con::Data {
+    reg_bit!(bipolar, set_bipolar, 0, 4, "Unipolar (`false`) or bipolar (`true`) coded output");
+    reg_bit!(refbuf_pos, set_refbuf_pos, 0, 3, "Enable REF+ input buffer");
+    reg_bit!(refbuf_neg, set_refbuf_neg, 0, 2, "Enable REF- input buffer");
+    reg_bit!(ainbuf_pos, set_ainbuf_pos, 0, 1, "Enable AIN+ input buffer");
+    reg_bit!(ainbuf_neg, set_ainbuf_neg, 0, 0, "Enable AIN- input buffer");
+    reg_bit!(burnout_en, 1, 7, "enables a 10 µA current source on the positive analog input selected and a 10 µA current sink on the negative analog input selected");
+    reg_bits!(ref_sel, set_ref_sel, 1, 4..=5, RefSource, "Select reference source for conversion");
+}
+
+def_reg!(FiltCon, u8, filt_con, 0x28, 2);
+impl filt_con::Data {
+    reg_bit!(sinc3_map, 0, 7, "If set, mapping of filter register changes to directly program the decimation rate of the sinc3 filter");
+    reg_bit!(enh_filt_en, set_enh_filt_en, 0, 3, "Enable postfilters for enhanced 50Hz and 60Hz rejection");
+    reg_bits!(enh_filt, set_enh_filt, 0, 0..=2, PostFilter, "Select postfilters for enhanced 50Hz and 60Hz rejection");
+    reg_bits!(order, set_order, 1, 5..=6, DigitalFilterOrder, "order of the digital filter that processes the modulator data");
+    reg_bits!(odr, set_odr, 1, 0..=4, "Output data rate");
+}
+
+def_reg!(Offset, u8, offset, 0x30, 3);
+impl offset::Data {
+    #[allow(unused)]
+    pub fn offset(&self) -> u32 {
+        (u32::from(self.0[0]) << 16) |
+        (u32::from(self.0[1]) << 8) |
+        u32::from(self.0[2])
+    }
+    #[allow(unused)]
+    pub fn set_offset(&mut self, value: u32) {
+        self.0[0] = (value >> 16) as u8;
+        self.0[1] = (value >> 8) as u8;
+        self.0[2] = value as u8;
+    }
+}
+
+def_reg!(Gain, u8, gain, 0x38, 3);
+impl gain::Data {
+    #[allow(unused)]
+    pub fn gain(&self) -> u32 {
+        (u32::from(self.0[0]) << 16) |
+        (u32::from(self.0[1]) << 8) |
+        u32::from(self.0[2])
+    }
+    #[allow(unused)]
+    pub fn set_gain(&mut self, value: u32) {
+        self.0[0] = (value >> 16) as u8;
+        self.0[1] = (value >> 8) as u8;
+        self.0[2] = value as u8;
+    }
+}
--- a/firmware/src/board/gpio.rs
+++ b/firmware/src/board/gpio.rs
@ -0,0 +1,82 @@
+use core::slice::{from_raw_parts, from_raw_parts_mut};
+use embedded_hal::digital::v2::{InputPin, OutputPin};
+
+pub trait Gpio where Self: Sized {
+    fn into_output(self) -> GpioOutput<Self>;
+    fn into_input(self) -> GpioInput<Self>;
+}
+
+pub struct GpioInput<PIN>(PIN);
+pub struct GpioOutput<PIN>(PIN);
+
+macro_rules! def_gpio {
+    ($PORT: tt, $PIN: tt, $idx: expr) => (
+        impl $PIN {
+            fn data(&self) -> &u32 {
+                let gpio = tm4c129x::$PORT::ptr();
+                let data = unsafe { from_raw_parts(gpio as *const _ as *mut u32, 0x100) };
+                &data[(1 << $idx) as usize]
+            }
+
+            fn data_mut(&mut self) -> &mut u32 {
+                let gpio = tm4c129x::$PORT::ptr();
+                let data = unsafe { from_raw_parts_mut(gpio as *const _ as *mut u32, 0x100) };
+                &mut data[(1 << $idx) as usize]
+            }
+        }
+
+        impl Gpio for $PIN {
+            fn into_output(self) -> GpioOutput<Self> {
+                let gpio = unsafe { &*tm4c129x::$PORT::ptr() };
+                gpio.dir.modify(|r, w| w.dir().bits(r.dir().bits() | (1 << $idx)));
+                gpio.den.modify(|r, w| w.den().bits(r.den().bits() | (1 << $idx)));
+                GpioOutput(self)
+            }
+            fn into_input(self) -> GpioInput<Self> {
+                let gpio = unsafe { &*tm4c129x::$PORT::ptr() };
+                gpio.dir.modify(|r, w| w.dir().bits(r.dir().bits() & !(1 << $idx)));
+                gpio.den.modify(|r, w| w.den().bits(r.den().bits() | (1 << $idx)));
+                GpioInput(self)
+            }
+        }
+
+        impl InputPin for GpioInput<$PIN> {
+            type Error = ();
+            fn is_high(&self) -> Result<bool, Self::Error> {
+                Ok(*self.0.data() != 0)
+            }
+            fn is_low(&self) -> Result<bool, Self::Error> {
+                Ok(*self.0.data() == 0)
+            }
+        }
+
+        impl OutputPin for GpioOutput<$PIN> {
+            type Error = ();
+            fn set_low(&mut self) -> Result<(), Self::Error> {
+                *self.0.data_mut() = 0;
+                Ok(())
+            }
+            fn set_high(&mut self) -> Result<(), Self::Error> {
+                *self.0.data_mut() = 0xFF;
+                Ok(())
+            }
+        }
+    )
+}
+
+pub struct PB4;
+def_gpio!(GPIO_PORTB_AHB, PB4, 4);
+pub struct PB5;
+def_gpio!(GPIO_PORTB_AHB, PB5, 5);
+pub struct PE4;
+def_gpio!(GPIO_PORTE_AHB, PE4, 4);
+pub struct PE5;
+def_gpio!(GPIO_PORTE_AHB, PE5, 5);
+pub struct PK1;
+def_gpio!(GPIO_PORTK, PK1, 1);
+pub struct PP2;
+def_gpio!(GPIO_PORTP, PP2, 2);
+pub struct PP3;
+def_gpio!(GPIO_PORTP, PP3, 3);
+pub struct PQ4;
+def_gpio!(GPIO_PORTQ, PQ4, 4);
--- a/firmware/src/board/mod.rs
+++ b/firmware/src/board/mod.rs
@ -0,0 +1,146 @@
+use cortex_m;
+use tm4c129x;
+
+pub mod gpio;
+pub mod softspi;
+pub mod systick;
+pub mod pwm;
+
+
+const UART_DIV: u32 = (((/*sysclk*/120_000_000 * 8) / /*baud*/115200) + 1) / 2;
+
+pub fn init() {
+    cortex_m::interrupt::free(|cs| {
+        let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
+
+        // Set up main oscillator
+        sysctl.moscctl.write(|w| w.noxtal().bit(false));
+        sysctl.moscctl.modify(|_, w| w.pwrdn().bit(false).oscrng().bit(true));
+
+        // Prepare flash for the high-freq clk
+        sysctl.memtim0.write(|w| unsafe { w.bits(0x01950195u32) });
+        sysctl.rsclkcfg.write(|w| unsafe { w.bits(0x80000000u32) });
+
+        // Set up PLL with fVCO=480 MHz
+        sysctl.pllfreq1.write(|w| w.q().bits(0).n().bits(4));
+        sysctl.pllfreq0.write(|w| w.mint().bits(96).pllpwr().bit(true));
+        sysctl.rsclkcfg.modify(|_, w| w.pllsrc().mosc().newfreq().bit(true));
+        while !sysctl.pllstat.read().lock().bit() {}
+
+        // Switch to PLL (sysclk=120MHz)
+        sysctl.rsclkcfg.write(|w| unsafe { w.bits(0b1_0_0_1_0011_0000_0000000000_0000000011) });
+
+        // Bring up GPIO ports A, B, D, E, F, G, K, L, M, P, Q
+        sysctl.rcgcgpio.modify(|_, w| {
+            w.r0().bit(true)
+             .r1().bit(true)
+             .r3().bit(true)
+             .r4().bit(true)
+             .r5().bit(true)
+             .r6().bit(true)
+             .r9().bit(true)
+             .r10().bit(true)
+             .r11().bit(true)
+             .r13().bit(true)
+             .r14().bit(true)
+        });
+        while !sysctl.prgpio.read().r0().bit() {}
+        while !sysctl.prgpio.read().r1().bit() {}
+        while !sysctl.prgpio.read().r3().bit() {}
+        while !sysctl.prgpio.read().r4().bit() {}
+        while !sysctl.prgpio.read().r5().bit() {}
+        while !sysctl.prgpio.read().r6().bit() {}
+        while !sysctl.prgpio.read().r9().bit() {}
+        while !sysctl.prgpio.read().r10().bit() {}
+        while !sysctl.prgpio.read().r11().bit() {}
+        while !sysctl.prgpio.read().r13().bit() {}
+        while !sysctl.prgpio.read().r14().bit() {}
+
+        // Set up UART0
+        let gpio_a = unsafe { &*tm4c129x::GPIO_PORTA_AHB::ptr() };
+        gpio_a.dir.write(|w| w.dir().bits(0b11));
+        gpio_a.den.write(|w| w.den().bits(0b11));
+        gpio_a.afsel.write(|w| w.afsel().bits(0b11));
+        gpio_a.pctl.write(|w| unsafe { w.pmc0().bits(1).pmc1().bits(1) });
+
+        sysctl.rcgcuart.modify(|_, w| w.r0().bit(true));
+        while !sysctl.pruart.read().r0().bit() {}
+
+        let uart_0 = unsafe { &*tm4c129x::UART0::ptr() };
+        uart_0.cc.write(|w| w.cs().sysclk());
+        uart_0.ibrd.write(|w| w.divint().bits((UART_DIV / 64) as u16));
+        uart_0.fbrd.write(|w| w.divfrac().bits((UART_DIV % 64) as u8));
+        uart_0.lcrh.write(|w| w.wlen()._8().fen().bit(true));
+        uart_0.ctl.write(|w| w.rxe().bit(true).txe().bit(true).uarten().bit(true));
+
+        // Set up PWMs
+        let gpio_m = unsafe { &*tm4c129x::GPIO_PORTM::ptr() };
+        // Output
+        gpio_m.dir.write(|w| w.dir().bits(0xff));
+        // Enable
+        gpio_m.den.write(|w| w.den().bits(0xff));
+        // Alternate function
+        gpio_m.afsel.write(|w| w.afsel().bits(0xff));
+        // Function: Timer PWM
+        gpio_m.pctl.write(|w| unsafe {
+            w
+                // t2ccp0
+                .pmc0().bits(3)
+                // t2ccp1
+                .pmc1().bits(3)
+                // t3ccp0
+                .pmc2().bits(3)
+                // t3ccp1
+                .pmc3().bits(3)
+                // t4ccp0
+                .pmc4().bits(3)
+                // t4ccp1
+                .pmc5().bits(3)
+                // t5ccp0
+                .pmc6().bits(3)
+                // t5ccp1
+                .pmc7().bits(3)
+        });
+
+        // Enable timers
+        sysctl.rcgctimer.write(|w| w
+            .r2().set_bit()
+            .r3().set_bit()
+            .r4().set_bit()
+            .r5().set_bit()
+        );
+        // Reset timers
+        sysctl.srtimer.write(|w| w
+            .r2().set_bit()
+            .r3().set_bit()
+            .r4().set_bit()
+            .r5().set_bit()
+        );
+        sysctl.srtimer.write(|w| w
+            .r2().clear_bit()
+            .r3().clear_bit()
+            .r4().clear_bit()
+            .r5().clear_bit()
+        );
+        fn timers_ready(sysctl: &tm4c129x::sysctl::RegisterBlock) -> bool {
+            let prtimer = sysctl.prtimer.read();
+            prtimer.r2().bit() &&
+                prtimer.r3().bit() &&
+                prtimer.r4().bit() &&
+                prtimer.r5().bit()
+        }
+        while !timers_ready(sysctl) {}
+
+        systick::init(cs);
+    });
+}
+
+pub fn get_mac_address() -> [u8; 6] {
+    let (userreg0, userreg1) = cortex_m::interrupt::free(|_cs| {
+        let flashctl = unsafe { &*tm4c129x::FLASH_CTRL::ptr() };
+        (flashctl.userreg0.read().bits(),
+         flashctl.userreg1.read().bits())
+    });
+    [userreg0 as u8, (userreg0 >> 8) as u8, (userreg0 >> 16) as u8,
+     userreg1 as u8, (userreg1 >> 8) as u8, (userreg1 >> 16) as u8]
+}
--- a/firmware/src/board/pwm.rs
+++ b/firmware/src/board/pwm.rs
@ -0,0 +1,138 @@
+use tm4c129x::{
+    TIMER2, TIMER3, TIMER4, TIMER5,
+};
+
+pub struct T2CCP0;
+pub struct T2CCP1;
+pub struct T3CCP0;
+pub struct T3CCP1;
+pub struct T4CCP0;
+pub struct T4CCP1;
+pub struct T5CCP0;
+pub struct T5CCP1;
+
+pub trait PwmPeripheral {
+    type ChannelA: PwmChannel;
+    type ChannelB: PwmChannel;
+    fn split() -> (Self::ChannelA, Self::ChannelB);
+}
+
+macro_rules! pwm_peripheral {
+    ($TIMER: ty, $A: tt, $B: tt) => {
+        impl PwmPeripheral for $TIMER {
+            type ChannelA = $A;
+            type ChannelB = $B;
+            fn split() -> (Self::ChannelA, Self::ChannelB) {
+                let regs = unsafe { &*Self::ptr() };
+                regs.cfg.write(|w| unsafe { w.bits(4) });
+
+                let mut a = $A;
+                a.configure();
+                let mut b = $B;
+                b.configure();
+                (a, b)
+            }
+        }
+    };
+}
+
+pwm_peripheral!(TIMER2, T2CCP0, T2CCP1);
+pwm_peripheral!(TIMER3, T3CCP0, T3CCP1);
+pwm_peripheral!(TIMER4, T4CCP0, T4CCP1);
+pwm_peripheral!(TIMER5, T5CCP0, T5CCP1);
+
+
+pub trait PwmChannel {
+    fn configure(&mut self);
+    fn get(&mut self) -> (u16, u16);
+    fn set(&mut self, width: u16, total: u16);
+}
+
+macro_rules! pwm_channel_a {
+    ($CHANNEL: ty, $TIMER: tt) => {
+        impl PwmChannel for $CHANNEL {
+            fn configure(&mut self) {
+                let timer = unsafe { &*tm4c129x::$TIMER::ptr() };
+                timer.tamr.modify(|_, w| unsafe {
+                    w
+                        .taams().bit(true)
+                        .tacmr().bit(false)
+                        .tamr().bits(2)
+                });
+                timer.ctl.modify(|_, w| {
+                    w
+                        .tapwml().bit(false)
+                });
+                // no prescaler
+                // no interrupts
+                timer.tailr.write(|w| unsafe { w.bits(0xFFFF) });
+                timer.tamatchr.write(|w| unsafe { w.bits(0x0) });
+                timer.ctl.modify(|_, w| {
+                    w
+                        .taen().bit(true)
+                });
+            }
+
+            fn get(&mut self) -> (u16, u16) {
+                let timer = unsafe { &*tm4c129x::$TIMER::ptr() };
+                (timer.tamatchr.read().bits() as u16,
+                 timer.tailr.read().bits() as u16)
+            }
+
+            fn set(&mut self, width: u16, total: u16) {
+                let timer = unsafe { &*tm4c129x::$TIMER::ptr() };
+                timer.tamatchr.write(|w| unsafe { w.bits(width.into()) });
+                timer.tailr.write(|w| unsafe { w.bits(total.into()) });
+            }
+        }
+    };
+}
+
+macro_rules! pwm_channel_b {
+    ($CHANNEL: ty, $TIMER: tt) => {
+        impl PwmChannel for $CHANNEL {
+            fn configure(&mut self) {
+                let timer = unsafe { &*tm4c129x::$TIMER::ptr() };
+                timer.tbmr.modify(|_, w| unsafe {
+                    w
+                        .tbams().bit(true)
+                        .tbcmr().bit(false)
+                        .tbmr().bits(2)
+                });
+                timer.ctl.modify(|_, w| {
+                    w
+                        .tbpwml().bit(false)
+                });
+                // no prescaler
+                // no interrupts
+                timer.tbilr.write(|w| unsafe { w.bits(0xFFFF) });
+                timer.tbmatchr.write(|w| unsafe { w.bits(0x0) });
+                timer.ctl.modify(|_, w| {
+                    w
+                        .tben().bit(true)
+                });
+            }
+
+            fn get(&mut self) -> (u16, u16) {
+                let timer = unsafe { &*tm4c129x::$TIMER::ptr() };
+                (timer.tbmatchr.read().bits() as u16,
+                 timer.tbilr.read().bits() as u16)
+            }
+
+            fn set(&mut self, width: u16, total: u16) {
+                let timer = unsafe { &*tm4c129x::$TIMER::ptr() };
+                timer.tbmatchr.write(|w| unsafe { w.bits(width.into()) });
+                timer.tbilr.write(|w| unsafe { w.bits(total.into()) });
+            }
+        }
+    };
+}
+
+pwm_channel_a!(T2CCP0, TIMER2);
+pwm_channel_b!(T2CCP1, TIMER2);
+pwm_channel_a!(T3CCP0, TIMER3);
+pwm_channel_b!(T3CCP1, TIMER3);
+pwm_channel_a!(T4CCP0, TIMER4);
+pwm_channel_b!(T4CCP1, TIMER4);
+pwm_channel_a!(T5CCP0, TIMER5);
+pwm_channel_b!(T5CCP1, TIMER5);
--- a/firmware/src/board/softspi.rs
+++ b/firmware/src/board/softspi.rs
@ -0,0 +1,148 @@
+use embedded_hal::spi::FullDuplex;
+use embedded_hal::digital::v2::{InputPin, OutputPin};
+use embedded_hal::blocking::spi::Transfer;
+use nb::Error::WouldBlock;
+
+/// Bit-banged Mode3 SPI
+pub struct SoftSpi<SCK, MOSI, MISO> {
+    sck: SCK,
+    mosi: MOSI,
+    miso: MISO,
+    state: State,
+    input: Option<u8>,
+}
+
+#[derive(PartialEq)]
+enum State {
+    Idle,
+    Transfer {
+        clock_phase: bool,
+        mask: u8,
+        output: u8,
+        input: u8,
+    },
+}
+
+impl<SCK: OutputPin, MOSI: OutputPin, MISO: InputPin> SoftSpi<SCK, MOSI, MISO> {
+    pub fn new(mut sck: SCK, mut mosi: MOSI, miso: MISO) -> Self {
+        let _ = sck.set_high();
+        let _ = mosi.set_low();
+        SoftSpi {
+            sck, mosi, miso,
+            state: State::Idle,
+            input: None,
+        }
+    }
+
+    /// Call this at twice the data rate
+    pub fn tick(&mut self) {
+        match self.state {
+            State::Idle => {}
+            State::Transfer { clock_phase: false,
+                              mask, output, input } => {
+                if output & mask != 0 {
+                    let _ = self.mosi.set_high();
+                } else {
+                    let _ = self.mosi.set_low();
+                }
+                let _ = self.sck.set_low();
+
+                self.state = State::Transfer {
+                    clock_phase: true,
+                    mask, output, input,
+                };
+            }
+            State::Transfer { clock_phase: true,
+                              mask, output, mut input } => {
+                if self.miso.is_high().unwrap_or(false) {
+                    input |= mask;
+                }
+                let _ = self.sck.set_high();
+
+                if mask != 1 {
+                    self.state = State::Transfer {
+                        clock_phase: false,
+                        mask: mask >> 1,
+                        output, input,
+                    };
+                } else {
+                    self.input = Some(input);
+                    self.state = State::Idle;
+                }
+            }
+        }
+    }
+
+    pub fn run<F: FnMut()>(&mut self, delay: &'_ mut F) {
+        while self.state != State::Idle {
+            self.tick();
+            delay();
+        }
+    }
+}
+
+impl<SCK: OutputPin, MOSI: OutputPin, MISO: InputPin> FullDuplex<u8> for SoftSpi<SCK, MOSI, MISO> {
+    type Error = ();
+
+    fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
+        match self.input.take() {
+            Some(input) =>
+                Ok(input),
+            None if self.state == State::Idle =>
+                Err(nb::Error::Other(())),
+            None =>
+                Err(WouldBlock),
+        }
+    }
+
+    fn send(&mut self, output: u8) -> Result<(), nb::Error<Self::Error>> {
+        match self.state {
+            State::Idle => {
+                self.state = State::Transfer {
+                    clock_phase: false,
+                    mask: 0x80,
+                    output,
+                    input: 0,
+                };
+                Ok(())
+            }
+            _ => Err(WouldBlock)
+        }
+    }
+}
+
+pub struct SyncSoftSpi<'d, SCK: OutputPin, MOSI: OutputPin, MISO: InputPin, D: FnMut()> {
+    spi: SoftSpi<SCK, MOSI, MISO>,
+    delay: &'d mut D,
+}
+
+impl<'d, SCK: OutputPin, MOSI: OutputPin, MISO: InputPin, D: FnMut()> SyncSoftSpi<'d, SCK, MOSI, MISO, D> {
+    pub fn new(spi: SoftSpi<SCK, MOSI, MISO>, delay: &'d mut D) -> Self {
+        SyncSoftSpi { spi, delay }
+    }
+
+    fn retry<R, E, F>(&mut self, f: &F) -> Result<R, E>
+    where
+        F: Fn(&'_ mut SoftSpi<SCK, MOSI, MISO>) -> Result<R, nb::Error<E>>
+    {
+        loop {
+            match f(&mut self.spi) {
+                Ok(r) => return Ok(r),
+                Err(nb::Error::Other(e)) => return Err(e),
+                Err(WouldBlock) => self.spi.run(self.delay),
+            }
+        }
+    }
+}
+
+impl<'d, SCK: OutputPin, MOSI: OutputPin, MISO: InputPin, D: FnMut()> Transfer<u8> for SyncSoftSpi<'d, SCK, MOSI, MISO, D> {
+    // TODO: proper type
+    type Error = ();
+    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
+        for b in words.iter_mut() {
+            self.retry(&|spi| spi.send(*b))?;
+            *b = self.retry(&|spi| spi.read())?;
+        }
+        Ok(words)
+    }
+}
--- a/firmware/src/board/systick.rs
+++ b/firmware/src/board/systick.rs
@ -0,0 +1,43 @@
+use core::cell::RefCell;
+use cortex_m::interrupt::Mutex;
+use cortex_m::peripheral::{SYST, syst::SystClkSource};
+use cortex_m_rt::exception;
+use bare_metal::CriticalSection;
+
+static mut TIME: Mutex<RefCell<u64>> = Mutex::new(RefCell::new(0));
+/// In HZ
+const RATE: u32 = 10;
+/// Period between two interrupts in ns
+const INTERVAL: u64 = 1_000_000 / RATE as u64;
+
+fn syst() -> &'static mut SYST {
+    #[allow(mutable_transmutes)]
+    unsafe { core::mem::transmute(&*SYST::ptr()) }
+}
+
+pub fn init(_cs: &CriticalSection) {
+    let syst = syst();
+    // syst.set_clock_source(SystClkSource::Core);
+    syst.set_clock_source(SystClkSource::External);
+    syst.set_reload(100 * SYST::get_ticks_per_10ms() / RATE);
+    syst.clear_current();
+    syst.enable_interrupt();
+    syst.enable_counter();
+}
+
+#[exception]
+unsafe fn SysTick() {
+    cortex_m::interrupt::free(|cs| {
+        TIME.borrow(cs).replace_with(|time| *time + INTERVAL);
+    });
+}
+
+pub fn get_time() -> u64 {
+    let base = cortex_m::interrupt::free(|cs| {
+        *unsafe { &mut TIME }.borrow(cs).borrow()
+    });
+    let syst_current = u64::from(SYST::get_current());
+    let syst_reload = u64::from(SYST::get_reload());
+    let precise = INTERVAL - (INTERVAL * syst_current / syst_reload);
+    base + u64::from(precise)
+}
--- a/firmware/src/command_parser.rs
+++ b/firmware/src/command_parser.rs
@ -0,0 +1,533 @@
+use core::fmt;
+use nom::{
+    IResult,
+    branch::alt,
+    bytes::complete::{is_a, tag, take_while1},
+    character::{is_digit, complete::{char, one_of}},
+    combinator::{complete, map, opt, value},
+    sequence::{preceded, separated_pair},
+    multi::{fold_many0, fold_many1},
+    error::ErrorKind,
+};
+use lexical_core as lexical;
+
+
+#[derive(Clone, Debug, PartialEq)]
+pub enum Error {
+    Parser(ErrorKind),
+    Incomplete,
+    UnexpectedInput(u8),
+    ParseNumber(lexical::Error)
+}
+
+impl<'t> From<nom::Err<(&'t [u8], ErrorKind)>> for Error {
+    fn from(e: nom::Err<(&'t [u8], ErrorKind)>) -> Self {
+        match e {
+            nom::Err::Incomplete(_) =>
+                Error::Incomplete,
+            nom::Err::Error((_, e)) =>
+                Error::Parser(e),
+            nom::Err::Failure((_, e)) =>
+                Error::Parser(e),
+        }
+    }
+}
+
+impl From<lexical::Error> for Error {
+    fn from(e: lexical::Error) -> Self {
+        Error::ParseNumber(e)
+    }
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, fmt: &mut fmt::Formatter) -> Result<(), fmt::Error> {
+        match self {
+            Error::Incomplete =>
+                "incomplete input".fmt(fmt),
+            Error::UnexpectedInput(c) => {
+                "unexpected input: ".fmt(fmt)?;
+                c.fmt(fmt)
+            }
+            Error::Parser(e) => {
+                "parser: ".fmt(fmt)?;
+                (e as &dyn core::fmt::Debug).fmt(fmt)
+            }
+            Error::ParseNumber(e) => {
+                "parsing number: ".fmt(fmt)?;
+                (e as &dyn core::fmt::Debug).fmt(fmt)
+            }
+        }
+    }
+}
+
+#[derive(Debug, Clone, PartialEq)]
+pub enum ShowCommand {
+    Input,
+    Reporting,
+    Pwm,
+    Pid,
+    SteinhartHart,
+    PostFilter,
+}
+
+#[derive(Debug, Clone, PartialEq)]
+pub enum PidParameter {
+    Target,
+    KP,
+    KI,
+    KD,
+    OutputMin,
+    OutputMax,
+    IntegralMin,
+    IntegralMax,
+}
+
+/// Steinhart-Hart equation parameter
+#[derive(Debug, Clone, PartialEq)]
+pub enum ShParameter {
+    A,
+    B,
+    C,
+    ParallelR,
+}
+
+#[derive(Debug, Clone, PartialEq)]
+pub struct PwmConfig {
+    pub width: u16,
+    pub total: u16,
+}
+
+#[derive(Debug, Clone, PartialEq)]
+pub enum PwmMode {
+    Manual(PwmConfig),
+    Pid,
+}
+
+#[derive(Debug, Clone, PartialEq)]
+pub enum PwmSetup {
+    ISet(PwmMode),
+    MaxIPos(PwmConfig),
+    MaxINeg(PwmConfig),
+    MaxV(PwmConfig),
+}
+
+#[derive(Debug, Clone, PartialEq)]
+pub enum Command {
+    Quit,
+    Show(ShowCommand),
+    Reporting(bool),
+    Pwm {
+        channel: usize,
+        setup: PwmSetup,
+    },
+    Pid {
+        channel: usize,
+        parameter: PidParameter,
+        value: f32,
+    },
+    SteinhartHart {
+        channel: usize,
+        parameter: ShParameter,
+        value: f32,
+    },
+    PostFilter {
+        channel: usize,
+        rate: f32,
+    },
+}
+
+fn end(input: &[u8]) -> IResult<&[u8], ()> {
+    complete(
+        fold_many0(
+            one_of("\r\n\t "),
+            (), |(), _| ()
+        )
+    )(input)
+}
+
+fn whitespace(input: &[u8]) -> IResult<&[u8], ()> {
+    fold_many1(char(' '), (), |(), _| ())(input)
+}
+
+fn unsigned(input: &[u8]) -> IResult<&[u8], Result<u16, Error>> {
+    take_while1(is_digit)(input)
+        .map(|(input, digits)| {
+            let result = lexical::parse(digits)
+                .map_err(|e| e.into());
+            (input, result)
+        })
+}
+
+fn float(input: &[u8]) -> IResult<&[u8], Result<f32, Error>> {
+    let (input, sign) = opt(is_a("-"))(input)?;
+    let negative = sign.is_some();
+    let (input, digits) = take_while1(|c| is_digit(c) || c == '.' as u8)(input)?;
+    let result = lexical::parse(digits)
+        .map(|result: f32| if negative { -result } else { result })
+        .map_err(|e| e.into());
+    Ok((input, result))
+}
+
+fn off_on(input: &[u8]) -> IResult<&[u8], bool> {
+    alt((value(false, tag("off")),
+         value(true, tag("on"))
+    ))(input)
+}
+
+fn channel(input: &[u8]) -> IResult<&[u8], usize> {
+    map(one_of("01"), |c| (c as usize) - ('0' as usize))(input)
+}
+
+fn report(input: &[u8]) -> IResult<&[u8], Command> {
+    preceded(
+        tag("report"),
+        alt((
+            preceded(
+                whitespace,
+                preceded(
+                    tag("mode"),
+                    alt((
+                        preceded(
+                            whitespace,
+                            // `report mode <on | off>` - Switch repoting mode
+                            map(off_on, Command::Reporting)
+                        ),
+                        // `report mode` - Show current reporting state
+                        value(Command::Show(ShowCommand::Reporting), end)
+                    ))
+                )),
+            // `report` - Report once
+            value(Command::Show(ShowCommand::Input), end)
+        ))
+    )(input)
+}
+
+/// `pwm ... <width> <total>` - Set pwm duty cycle
+fn pwm_config(input: &[u8]) -> IResult<&[u8], Result<PwmConfig, Error>> {
+    let (input, width) = unsigned(input)?;
+    let width = match width {
+        Ok(width) => width,
+        Err(e) => return Ok((input, Err(e.into()))),
+    };
+    let (input, _) = whitespace(input)?;
+    let (input, total) = unsigned(input)?;
+    let total = match total {
+        Ok(total) => total,
+        Err(e) => return Ok((input, Err(e.into()))),
+    };
+    Ok((input, Ok(PwmConfig { width, total })))
+}
+
+fn pwm_setup(input: &[u8]) -> IResult<&[u8], Result<PwmSetup, Error>> {
+    alt((
+        map(
+            preceded(
+                tag("max_i_pos"),
+                preceded(
+                    whitespace,
+                    pwm_config
+                )
+            ),
+            |result| result.map(PwmSetup::MaxIPos)
+        ),
+        map(
+            preceded(
+                tag("max_i_neg"),
+                preceded(
+                    whitespace,
+                    pwm_config
+                )
+            ),
+            |result| result.map(PwmSetup::MaxINeg)
+        ),
+        map(
+            preceded(
+                tag("max_v"),
+                preceded(
+                    whitespace,
+                    pwm_config
+                )
+            ),
+            |result| result.map(PwmSetup::MaxV)
+        ),
+        map(pwm_config, |result| result.map(|config| {
+            PwmSetup::ISet(PwmMode::Manual(config))
+        }))
+    ))(input)
+}
+
+/// `pwm <0-1> pid` - Set PWM to be controlled by PID
+fn pwm_pid(input: &[u8]) -> IResult<&[u8], Result<PwmSetup, Error>> {
+    value(Ok(PwmSetup::ISet(PwmMode::Pid)), tag("pid"))(input)
+}
+
+fn pwm(input: &[u8]) -> IResult<&[u8], Result<Command, Error>> {
+    let (input, _) = tag("pwm")(input)?;
+    alt((
+        preceded(
+            whitespace,
+            map(
+                separated_pair(
+                    channel,
+                    whitespace,
+                    alt((
+                        pwm_pid,
+                        pwm_setup
+                    ))
+                ),
+                |(channel, setup)| setup.map(|setup| Command::Pwm { channel, setup })
+            )
+        ),
+        value(Ok(Command::Show(ShowCommand::Pwm)), end)
+    ))(input)
+}
+
+/// `pid <0-1> <parameter> <value>`
+fn pid_parameter(input: &[u8]) -> IResult<&[u8], Result<Command, Error>> {
+    let (input, channel) = channel(input)?;
+    let (input, _) = whitespace(input)?;
+    let (input, parameter) =
+        alt((value(PidParameter::Target, tag("target")),
+             value(PidParameter::KP, tag("kp")),
+             value(PidParameter::KI, tag("ki")),
+             value(PidParameter::KD, tag("kd")),
+             value(PidParameter::OutputMin, tag("output_min")),
+             value(PidParameter::OutputMax, tag("output_max")),
+             value(PidParameter::IntegralMin, tag("integral_min")),
+             value(PidParameter::IntegralMax, tag("integral_max"))
+        ))(input)?;
+    let (input, _) = whitespace(input)?;
+    let (input, value) = float(input)?;
+    let result = value
+        .map(|value| Command::Pid { channel, parameter, value });
+    Ok((input, result))
+}
+
+/// `pid` | `pid <pid_parameter>`
+fn pid(input: &[u8]) -> IResult<&[u8], Result<Command, Error>> {
+    let (input, _) = tag("pid")(input)?;
+    alt((
+        preceded(
+            whitespace,
+            pid_parameter
+        ),
+        value(Ok(Command::Show(ShowCommand::Pid)), end)
+    ))(input)
+}
+
+/// `s-h <0-1> <parameter> <value>`
+fn steinhart_hart_parameter(input: &[u8]) -> IResult<&[u8], Result<Command, Error>> {
+    let (input, channel) = channel(input)?;
+    let (input, _) = whitespace(input)?;
+    let (input, parameter) =
+        alt((value(ShParameter::A, tag("a")),
+             value(ShParameter::B, tag("b")),
+             value(ShParameter::C, tag("c")),
+             value(ShParameter::ParallelR, tag("parallel_r"))
+        ))(input)?;
+    let (input, _) = whitespace(input)?;
+    let (input, value) = float(input)?;
+    let result = value
+        .map(|value| Command::SteinhartHart { channel, parameter, value });
+    Ok((input, result))
+}
+
+/// `s-h` | `s-h <steinhart_hart_parameter>`
+fn steinhart_hart(input: &[u8]) -> IResult<&[u8], Result<Command, Error>> {
+    let (input, _) = tag("s-h")(input)?;
+    alt((
+        preceded(
+            whitespace,
+            steinhart_hart_parameter
+        ),
+        value(Ok(Command::Show(ShowCommand::SteinhartHart)), end)
+    ))(input)
+}
+
+fn postfilter(input: &[u8]) -> IResult<&[u8], Result<Command, Error>> {
+    let (input, _) = tag("postfilter")(input)?;
+    alt((
+        preceded(
+            whitespace,
+            |input| {
+                let (input, channel) = channel(input)?;
+                let (input, _) = whitespace(input)?;
+                let (input, _) = tag("rate")(input)?;
+                let (input, _) = whitespace(input)?;
+                let (input, rate) = float(input)?;
+                let result = rate
+                    .map(|rate| Command::PostFilter {
+                        channel, rate,
+                    });
+                Ok((input, result))
+            }
+        ),
+        value(Ok(Command::Show(ShowCommand::PostFilter)), end)
+    ))(input)
+}
+
+fn command(input: &[u8]) -> IResult<&[u8], Result<Command, Error>> {
+    alt((value(Ok(Command::Quit), tag("quit")),
+         map(report, Ok),
+         pwm,
+         pid,
+         steinhart_hart,
+         postfilter,
+    ))(input)
+}
+
+impl Command {
+    pub fn parse(input: &[u8]) -> Result<Self, Error> {
+        match command(input) {
+            Ok((b"", result)) =>
+                result,
+            Ok((input_remain, _)) =>
+                Err(Error::UnexpectedInput(input_remain[0])),
+            Err(e) =>
+                Err(e.into()),
+        }
+    }
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    #[test]
+    fn parse_quit() {
+        let command = Command::parse(b"quit");
+        assert_eq!(command, Ok(Command::Quit));
+    }
+
+    #[test]
+    fn parse_report() {
+        let command = Command::parse(b"report");
+        assert_eq!(command, Ok(Command::Show(ShowCommand::Input)));
+    }
+
+    #[test]
+    fn parse_report_mode() {
+        let command = Command::parse(b"report mode");
+        assert_eq!(command, Ok(Command::Show(ShowCommand::Reporting)));
+    }
+
+    #[test]
+    fn parse_report_mode_on() {
+        let command = Command::parse(b"report mode on");
+        assert_eq!(command, Ok(Command::Reporting(true)));
+    }
+
+    #[test]
+    fn parse_report_mode_off() {
+        let command = Command::parse(b"report mode off");
+        assert_eq!(command, Ok(Command::Reporting(false)));
+    }
+
+    #[test]
+    fn parse_pwm_manual() {
+        let command = Command::parse(b"pwm 1 16383 65535");
+        assert_eq!(command, Ok(Command::Pwm {
+            channel: 1,
+            setup: PwmSetup::ISet(PwmMode::Manual(PwmConfig {
+                width: 16383,
+                total: 65535,
+            })),
+        }));
+    }
+
+    #[test]
+    fn parse_pwm_pid() {
+        let command = Command::parse(b"pwm 0 pid");
+        assert_eq!(command, Ok(Command::Pwm {
+            channel: 0,
+            setup: PwmSetup::ISet(PwmMode::Pid),
+        }));
+    }
+
+    #[test]
+    fn parse_pwm_max_i_pos() {
+        let command = Command::parse(b"pwm 0 max_i_pos 7 13");
+        assert_eq!(command, Ok(Command::Pwm {
+            channel: 0,
+            setup: PwmSetup::MaxIPos(PwmConfig {
+                width: 7,
+                total: 13,
+            }),
+        }));
+    }
+
+    #[test]
+    fn parse_pwm_max_i_neg() {
+        let command = Command::parse(b"pwm 0 max_i_neg 128 65535");
+        assert_eq!(command, Ok(Command::Pwm {
+            channel: 0,
+            setup: PwmSetup::MaxINeg(PwmConfig {
+                width: 128,
+                total: 65535,
+            }),
+        }));
+    }
+
+    #[test]
+    fn parse_pwm_max_v() {
+        let command = Command::parse(b"pwm 0 max_v 32768 65535");
+        assert_eq!(command, Ok(Command::Pwm {
+            channel: 0,
+            setup: PwmSetup::MaxV(PwmConfig {
+                width: 32768,
+                total: 65535,
+            }),
+        }));
+    }
+
+    #[test]
+    fn parse_pid() {
+        let command = Command::parse(b"pid");
+        assert_eq!(command, Ok(Command::Show(ShowCommand::Pid)));
+    }
+
+    #[test]
+    fn parse_pid_target() {
+        let command = Command::parse(b"pid 0 target 36.5");
+        assert_eq!(command, Ok(Command::Pid {
+            channel: 0,
+            parameter: PidParameter::Target,
+            value: 36.5,
+        }));
+    }
+
+    #[test]
+    fn parse_pid_integral_max() {
+        let command = Command::parse(b"pid 1 integral_max 2000");
+        assert_eq!(command, Ok(Command::Pid {
+            channel: 1,
+            parameter: PidParameter::IntegralMax,
+            value: 2000.0,
+        }));
+    }
+
+    #[test]
+    fn parse_steinhart_hart() {
+        let command = Command::parse(b"s-h");
+        assert_eq!(command, Ok(Command::Show(ShowCommand::SteinhartHart)));
+    }
+
+    #[test]
+    fn parse_steinhart_hart_parallel_r() {
+        let command = Command::parse(b"s-h 1 parallel_r 23.05");
+        assert_eq!(command, Ok(Command::SteinhartHart {
+            channel: 1,
+            parameter: ShParameter::ParallelR,
+            value: 23.05,
+        }));
+    }
+
+    #[test]
+    fn parse_postfilter_rate() {
+        let command = Command::parse(b"postfilter 0 rate 21");
+        assert_eq!(command, Ok(Command::PostFilter {
+            channel: 0,
+            rate: 21.0,
+        }));
+    }
+}
--- a/firmware/src/ethmac.rs
+++ b/firmware/src/ethmac.rs
@ -0,0 +1,447 @@
+use core::{slice, cmp};
+use cortex_m::{self, asm::delay};
+use tm4c129x;
+use smoltcp::Result;
+use smoltcp::time::Instant;
+use smoltcp::wire::EthernetAddress;
+use smoltcp::phy;
+
+const EPHY_BMCR: u8 =           0x00; // Ethernet PHY Basic Mode Control
+#[allow(dead_code)]
+const EPHY_BMSR: u8 =           0x01; // Ethernet PHY Basic Mode Status
+const EPHY_ID1: u8 =            0x02; // Ethernet PHY Identifier Register 1
+const EPHY_ID2: u8 =            0x03; // Ethernet PHY Identifier Register 2
+
+const EPHY_REGCTL: u8 =         0x0D; // Ethernet PHY Register Control
+const EPHY_ADDAR: u8 =          0x0E; // Ethernet PHY Address or Data
+
+const EPHY_LEDCFG: u8 =         0x25; // Ethernet PHY LED Configuration
+
+// Transmit DMA descriptor flags
+const EMAC_TDES0_OWN: u32 =     0x80000000; // Indicates that the descriptor is owned by the DMA
+const EMAC_TDES0_LS: u32 =      0x20000000; // Last Segment
+const EMAC_TDES0_FS: u32 =      0x10000000; // First Segment
+const EMAC_TDES0_TCH: u32 =     0x00100000; // Second Address Chained
+#[allow(dead_code)]
+const EMAC_TDES1_TBS1: u32 =    0x00001FFF; // Transmit Buffer 1 Size
+
+// Receive DMA descriptor flags
+const EMAC_RDES0_OWN: u32 =     0x80000000; // indicates that the descriptor is owned by the DMA
+const EMAC_RDES0_FL: u32 =      0x3FFF0000; // Frame Length
+const EMAC_RDES0_ES: u32 =      0x00008000; // Error Summary
+const EMAC_RDES0_FS: u32 =      0x00000200; // First Descriptor
+const EMAC_RDES0_LS: u32 =      0x00000100; // Last Descriptor
+const EMAC_RDES1_RCH: u32 =     0x00004000; // Second Address Chained
+const EMAC_RDES1_RBS1: u32 =    0x00001FFF; // Receive Buffer 1 Size
+
+const ETH_DESC_U32_SIZE: usize =    8;
+const ETH_TX_BUFFER_COUNT: usize =  2;
+const ETH_TX_BUFFER_SIZE: usize =   1536;
+const ETH_RX_BUFFER_COUNT: usize =  3;
+const ETH_RX_BUFFER_SIZE: usize =   1536;
+
+fn phy_read(reg_addr: u8) -> u16 {
+    cortex_m::interrupt::free(|_cs| {
+        let emac0 = unsafe { &*tm4c129x::EMAC0::ptr() };
+
+        // Make sure the MII is idle
+        while emac0.miiaddr.read().miib().bit() {};
+
+        // Tell the MAC to read the given PHY register
+        unsafe {
+            emac0.miiaddr.write(|w| {
+                    w.cr()._100_150()
+                    .mii().bits(reg_addr & 0x1F)
+                    .miib().bit(true)
+            });
+        }
+
+        // Wait for the read to complete
+        while emac0.miiaddr.read().miib().bit() {};
+
+        emac0.miidata.read().data().bits()
+    })
+}
+
+fn phy_write(reg_addr: u8, reg_data: u16) {
+    cortex_m::interrupt::free(|_cs| {
+        let emac0 = unsafe { &*tm4c129x::EMAC0::ptr() };
+
+        // Make sure the MII is idle
+        while emac0.miiaddr.read().miib().bit() {};
+
+        unsafe {
+            emac0.miidata.write(|w| {
+                w.data().bits(reg_data)
+            });
+
+            // Tell the MAC to write the given PHY register
+            emac0.miiaddr.write(|w| {
+                    w.cr()._100_150()
+                    .mii().bits(reg_addr & 0x1F)
+                    .miiw().bit(true)
+                    .miib().bit(true)
+            });
+        }
+
+        // Wait for the read to complete
+        while emac0.miiaddr.read().miib().bit() {};
+    })
+}
+
+// Writes a value to an extended PHY register in MMD address space
+fn phy_write_ext(reg_addr: u8, reg_data: u16) {
+    phy_write(EPHY_REGCTL, 0x001F); // set address (datasheet page 1612)
+    phy_write(EPHY_ADDAR, reg_addr as u16);
+    phy_write(EPHY_REGCTL, 0x401F); // set write mode
+    phy_write(EPHY_ADDAR, reg_data);
+}
+
+struct RxRing {
+    desc_buf: [u32; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
+    cur_desc: usize,
+    counter: u32,
+    pkt_buf: [u8; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
+}
+
+impl RxRing {
+    fn new() -> RxRing {
+        RxRing {
+            desc_buf: [0; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
+            cur_desc: 0,
+            counter: 0,
+            pkt_buf: [0; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
+        }
+    }
+
+    fn init(&mut self) {
+        // Initialize RX DMA descriptors
+        for x in 0..ETH_RX_BUFFER_COUNT {
+            let p = x * ETH_DESC_U32_SIZE;
+            let r = x * ETH_RX_BUFFER_SIZE;
+
+            // The descriptor is initially owned by the DMA
+            self.desc_buf[p + 0] = EMAC_RDES0_OWN;
+            // Use chain structure rather than ring structure
+            self.desc_buf[p + 1] =
+                EMAC_RDES1_RCH | ((ETH_RX_BUFFER_SIZE as u32) & EMAC_RDES1_RBS1);
+            // Receive buffer address
+            self.desc_buf[p + 2] = (&self.pkt_buf[r] as *const u8) as u32;
+            // Next descriptor address
+            if x != ETH_RX_BUFFER_COUNT - 1 {
+                self.desc_buf[p + 3] =
+                    (&self.desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
+            } else {
+                self.desc_buf[p + 3] =
+                    (&self.desc_buf[0] as *const u32) as u32;
+            }
+            // Extended status
+            self.desc_buf[p + 4] = 0;
+            // Reserved field
+            self.desc_buf[p + 5] = 0;
+            // Transmit frame time stamp
+            self.desc_buf[p + 6] = 0;
+            self.desc_buf[p + 7] = 0;
+        }
+    }
+
+    fn buf_owned(&self) -> bool {
+        self.desc_buf[self.cur_desc + 0] & EMAC_RDES0_OWN == 0
+    }
+
+    fn buf_valid(&self) -> bool {
+        self.desc_buf[self.cur_desc + 0] &
+            (EMAC_RDES0_FS | EMAC_RDES0_LS | EMAC_RDES0_ES) ==
+            (EMAC_RDES0_FS | EMAC_RDES0_LS)
+    }
+
+    unsafe fn buf_as_slice<'a>(&self) -> &'a mut [u8] {
+        let len  = (self.desc_buf[self.cur_desc + 0] & EMAC_RDES0_FL) >> 16;
+        let len  = cmp::min(len as usize, ETH_RX_BUFFER_SIZE);
+        let addr = self.desc_buf[self.cur_desc + 2] as *mut u8;
+        slice::from_raw_parts_mut(addr, len)
+    }
+
+    fn buf_release(&mut self) {
+        self.cur_desc += ETH_DESC_U32_SIZE;
+        if self.cur_desc == self.desc_buf.len() {
+            self.cur_desc = 0;
+        }
+        self.counter += 1;
+
+        self.desc_buf[self.cur_desc + 0] = EMAC_RDES0_OWN;
+    }
+}
+
+struct TxRing {
+    desc_buf: [u32; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
+    cur_desc: usize,
+    counter: u32,
+    pkt_buf: [u8; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
+}
+
+impl TxRing {
+    fn new() -> TxRing {
+        TxRing {
+            desc_buf: [0; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
+            cur_desc: 0,
+            counter: 0,
+            pkt_buf: [0; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
+        }
+    }
+
+    fn init(&mut self) {
+        // Initialize TX DMA descriptors
+        for x in 0..ETH_TX_BUFFER_COUNT {
+            let p = x * ETH_DESC_U32_SIZE;
+            let r = x * ETH_TX_BUFFER_SIZE;
+
+            // Initialize transmit flags
+            self.desc_buf[p + 0] = 0;
+            // Initialize transmit buffer size
+            self.desc_buf[p + 1] = 0;
+            // Transmit buffer address
+            self.desc_buf[p + 2] = (&self.pkt_buf[r] as *const u8) as u32;
+            // Next descriptor address
+            if x != ETH_TX_BUFFER_COUNT - 1 {
+                self.desc_buf[p + 3] =
+                    (&self.desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
+            } else {
+                self.desc_buf[p + 3] =
+                    (&self.desc_buf[0] as *const u32) as u32;
+            }
+            // Reserved fields
+            self.desc_buf[p + 4] = 0;
+            self.desc_buf[p + 5] = 0;
+            // Transmit frame time stamp
+            self.desc_buf[p + 6] = 0;
+            self.desc_buf[p + 7] = 0;
+        }
+    }
+
+    fn buf_owned(&self) -> bool {
+        self.desc_buf[self.cur_desc + 0] & EMAC_TDES0_OWN == 0
+    }
+
+    unsafe fn buf_as_slice<'a>(&mut self, len: usize) -> &'a mut [u8] {
+        let len = cmp::min(len, ETH_TX_BUFFER_SIZE);
+        self.desc_buf[self.cur_desc + 1] = len as u32;
+        let addr = self.desc_buf[self.cur_desc + 2] as *mut u8;
+        slice::from_raw_parts_mut(addr, len)
+    }
+
+    fn buf_release(&mut self) {
+        self.desc_buf[self.cur_desc + 0] =
+            EMAC_TDES0_OWN | EMAC_TDES0_LS | EMAC_TDES0_FS | EMAC_TDES0_TCH;
+
+        cortex_m::interrupt::free(|_cs| {
+            let emac0 = unsafe { &*tm4c129x::EMAC0::ptr() };
+            // Clear TU flag to resume processing
+            emac0.dmaris.write(|w| w.tu().bit(true));
+            // Instruct the DMA to poll the transmit descriptor list
+            unsafe { emac0.txpolld.write(|w| w.tpd().bits(0)); }
+        });
+
+        self.cur_desc += ETH_DESC_U32_SIZE;
+        if self.cur_desc == self.desc_buf.len() {
+            self.cur_desc = 0;
+        }
+        self.counter += 1;
+    }
+}
+
+pub struct Device {
+    rx: RxRing,
+    tx: TxRing,
+}
+
+impl Device {
+    pub fn new() -> Device {
+        Device {
+            rx: RxRing::new(),
+            tx: TxRing::new(),
+        }
+    }
+
+    // After `init` is called, `Device` shall not be moved.
+    pub unsafe fn init(&mut self, mac: EthernetAddress) {
+        self.rx.init();
+        self.tx.init();
+
+        cortex_m::interrupt::free(|_cs| {
+            let sysctl = &*tm4c129x::SYSCTL::ptr();
+            let emac0 = &*tm4c129x::EMAC0::ptr();
+
+            sysctl.rcgcemac.modify(|_, w| w.r0().bit(true)); // Bring up MAC
+            sysctl.sremac.modify(|_, w| w.r0().bit(true)); // Activate MAC reset
+            delay(16);
+            sysctl.sremac.modify(|_, w| w.r0().bit(false)); // Dectivate MAC reset
+
+            sysctl.rcgcephy.modify(|_, w| w.r0().bit(true)); // Bring up PHY
+            sysctl.srephy.modify(|_, w| w.r0().bit(true)); // Activate PHY reset
+            delay(16);
+            sysctl.srephy.modify(|_, w| w.r0().bit(false)); // Dectivate PHY reset
+
+            while !sysctl.premac.read().r0().bit() {} // Wait for the MAC to come out of reset
+            while !sysctl.prephy.read().r0().bit() {} // Wait for the PHY to come out of reset
+            delay(10000);
+
+            emac0.dmabusmod.modify(|_, w| w.swr().bit(true)); // Reset MAC DMA
+            while emac0.dmabusmod.read().swr().bit() {} // Wait for the MAC DMA to come out of reset
+            delay(1000);
+
+            emac0.miiaddr.write(|w| w.cr()._100_150()); // Set the MII CSR clock speed.
+
+            // Checking PHY
+            if  (phy_read(EPHY_ID1) != 0x2000) | (phy_read(EPHY_ID2) != 0xA221) {
+                panic!("PHY ID error!");
+            }
+
+            // Reset PHY transceiver
+            phy_write(EPHY_BMCR, 1); // Initiate MII reset
+            while (phy_read(EPHY_BMCR) & 1) == 1 {}; // Wait for the reset to be completed
+
+            // Configure PHY LEDs
+            phy_write_ext(EPHY_LEDCFG, 0x0008); // LED0 Link OK/Blink on TX/RX Activity
+
+            // Tell the PHY to start an auto-negotiation cycle
+            phy_write(EPHY_BMCR, 0b00010010_00000000); // ANEN and RESTARTAN
+
+            // Set the DMA operation mode
+            emac0.dmaopmode.write(|w|
+                w.rsf().bit(true) // Receive Store and Forward
+                 .tsf().bit(true) // Transmit Store and Forward
+                 .ttc()._64() // Transmit Threshold Control
+                 .rtc()._64() // Receive Threshold Control
+            );
+
+            // Set the bus mode register.
+            emac0.dmabusmod.write(|w|
+                w.atds().bit(true)
+                 .aal().bit(true) // Address Aligned Beats
+                 .usp().bit(true) // Use Separate Programmable Burst Length ???
+                 .rpbl().bits(1) // RX DMA Programmable Burst Length
+                 .pbl().bits(1) // Programmable Burst Length
+                 .pr().bits(0) // Priority Ratio 1:1
+            );
+
+            // Disable all the MMC interrupts as these are enabled by default at reset.
+            emac0.mmcrxim.write(|w| w.bits(0xFFFFFFFF));
+            emac0.mmctxim.write(|w| w.bits(0xFFFFFFFF));
+
+            // Set MAC configuration options
+            emac0.cfg.write(|w|
+                w.dupm().bit(true) // MAC operates in full-duplex mode
+                 .ipc().bit(true) // Checksum Offload Enable
+                 .prelen()._7() // 7 bytes of preamble
+                 .ifg()._96() // 96 bit times
+                 .bl()._1024() // Back-Off Limit 1024
+                 .ps().bit(true) // ?
+            );
+
+            // Set the maximum receive frame size
+            emac0.wdogto.write(|w|
+                w.bits(0) // ??? no use watchdog
+            );
+
+            // Set the MAC address
+            emac0.addr0l.write(|w|
+                w.addrlo().bits(  mac.0[0] as u32 |
+                                ((mac.0[1] as u32) <<  8) |
+                                ((mac.0[2] as u32) << 16) |
+                                ((mac.0[3] as u32) << 24))
+            );
+            emac0.addr0h.write(|w|
+                w.addrhi().bits(  mac.0[4] as u16 |
+                                ((mac.0[5] as u16) << 8))
+            );
+
+            // Set MAC filtering options (?)
+            emac0.framefltr.write(|w|
+                w.hpf().bit(true) // Hash or Perfect Filter
+                //.hmc().bit(true) // Hash Multicast ???
+                 .pm().bit(true) // Pass All Multicast
+            );
+
+            // Initialize hash table
+            emac0.hashtbll.write(|w| w.htl().bits(0));
+            emac0.hashtblh.write(|w| w.hth().bits(0));
+
+            emac0.flowctl.write(|w| w.bits(0)); // Disable flow control ???
+
+            emac0.txdladdr.write(|w| /*unsafe*/ {
+                w.bits((&mut self.tx.desc_buf[0] as *mut u32) as u32)
+            });
+            emac0.rxdladdr.write(|w| /*unsafe*/ {
+                w.bits((&mut self.rx.desc_buf[0] as *mut u32) as u32)
+            });
+
+            // Manage MAC transmission and reception
+            emac0.cfg.modify(|_, w|
+                w.re().bit(true) // Receiver Enable
+                 .te().bit(true) // Transmiter Enable
+            );
+
+            // Manage DMA transmission and reception
+            emac0.dmaopmode.modify(|_, w|
+                w.sr().bit(true) // Start Receive
+                 .st().bit(true) // Start Transmit
+            );
+        });
+    }
+}
+
+impl<'a, 'b> phy::Device<'a> for &'b mut Device {
+    type RxToken = RxToken<'a>;
+    type TxToken = TxToken<'a>;
+
+    fn capabilities(&self) -> phy::DeviceCapabilities {
+        let mut capabilities = phy::DeviceCapabilities::default();
+        capabilities.max_transmission_unit = 1500;
+        capabilities.max_burst_size = Some(ETH_RX_BUFFER_COUNT);
+        capabilities
+    }
+
+    fn receive(&mut self) -> Option<(RxToken, TxToken)> {
+        // Skip all queued packets with errors.
+        while self.rx.buf_owned() && !self.rx.buf_valid() {
+            self.rx.buf_release()
+        }
+
+        if !(self.rx.buf_owned() && self.tx.buf_owned()) {
+            return None
+        }
+
+        Some((RxToken(&mut self.rx), TxToken(&mut self.tx)))
+    }
+
+    fn transmit(&mut self) -> Option<TxToken> {
+        if !self.tx.buf_owned() {
+            return None
+        }
+
+        Some(TxToken(&mut self.tx))
+    }
+}
+
+pub struct RxToken<'a>(&'a mut RxRing);
+
+impl<'a> phy::RxToken for RxToken<'a> {
+    fn consume<R, F>(self, _timestamp: Instant, f: F) -> Result<R>
+            where F: FnOnce(&mut [u8]) -> Result<R> {
+        let result = f(unsafe { self.0.buf_as_slice() });
+        self.0.buf_release();
+        result
+    }
+}
+
+pub struct TxToken<'a>(&'a mut TxRing);
+
+impl<'a> phy::TxToken for TxToken<'a> {
+    fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> Result<R>
+            where F: FnOnce(&mut [u8]) -> Result<R> {
+        let result = f(unsafe { self.0.buf_as_slice(len) });
+        self.0.buf_release();
+        result
+    }
+}
--- a/firmware/src/logo.svg.gz
+++ b/firmware/src/logo.svg.gz
--- a/firmware/src/main.rs
+++ b/firmware/src/main.rs
@ -0,0 +1,516 @@
+#![feature(const_fn, proc_macro_hygiene)]
+#![cfg_attr(not(test), no_std)]
+#![cfg_attr(not(test), no_main)]
+
+use cortex_m_rt::entry;
+use core::fmt::{self, Write};
+use smoltcp::time::Instant;
+use smoltcp::wire::{IpCidr, IpAddress, EthernetAddress};
+use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
+use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
+use cortex_m_semihosting::hio;
+
+#[macro_export]
+macro_rules! print {
+    ($($arg:tt)*) => ({
+        use core::fmt::Write;
+        write!($crate::UART0, $($arg)*).unwrap()
+    })
+}
+
+#[macro_export]
+macro_rules! println {
+    ($fmt:expr) => (print!(concat!($fmt, "\n")));
+    ($fmt:expr, $($arg:tt)*) => (print!(concat!($fmt, "\n"), $($arg)*));
+}
+
+#[cfg(not(test))]
+#[no_mangle] // https://github.com/rust-lang/rust/issues/{38281,51647}
+#[panic_handler]
+pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
+    println!("{}", info);
+    let mut stdout = hio::hstdout().unwrap();
+    let _ = writeln!(stdout, "{}", info);
+    loop {}
+}
+
+mod board;
+use self::board::{
+    gpio::Gpio,
+    systick::get_time,
+};
+mod ethmac;
+mod command_parser;
+use command_parser::{Command, ShowCommand, PwmSetup, PwmMode, PwmConfig};
+mod session;
+use self::session::{Session, SessionOutput};
+mod ad7172;
+mod pid;
+mod tec;
+use tec::{Tec, TecPin};
+mod steinhart_hart;
+use steinhart_hart as sh;
+
+pub struct UART0;
+
+impl fmt::Write for UART0 {
+    fn write_str(&mut self, s: &str) -> Result<(), fmt::Error> {
+        let uart_0 = unsafe { &*tm4c129x::UART0::ptr() };
+        for c in s.bytes() {
+            while uart_0.fr.read().txff().bit() {}
+            uart_0.dr.write(|w| w.data().bits(c))
+        }
+        Ok(())
+    }
+}
+
+const TCP_RX_BUFFER_SIZE: usize = 256;
+const TCP_TX_BUFFER_SIZE: usize = 8192;
+
+
+macro_rules! create_socket_storage {
+    ($rx_storage:ident, $tx_storage:ident) => (
+        let mut $rx_storage = [0; TCP_RX_BUFFER_SIZE];
+        let mut $tx_storage = [0; TCP_TX_BUFFER_SIZE];
+    )
+}
+
+macro_rules! create_socket {
+    ($set:ident, $rx_storage:ident, $tx_storage:ident, $target:ident) => (
+        let tcp_rx_buffer = TcpSocketBuffer::new(&mut $rx_storage[..]);
+        let tcp_tx_buffer = TcpSocketBuffer::new(&mut $tx_storage[..]);
+        let tcp_socket = TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
+        let $target = $set.add(tcp_socket);
+    )
+}
+
+const VCC: f32 = 3.3;
+
+const PWM_PID_WIDTH: u16 = 0xffff;
+const PWM_MAX: f32 = PWM_PID_WIDTH as f32;
+
+const DEFAULT_PID_PARAMETERS: pid::Parameters = pid::Parameters {
+    kp: 0.5 * PWM_MAX,
+    ki: 0.05 * PWM_MAX,
+    kd: 0.45 * PWM_MAX,
+    output_min: 0.0,
+    output_max: PWM_MAX,
+    integral_min: 0.0,
+    integral_max: PWM_MAX,
+};
+
+const DEFAULT_SH_PARAMETERS: sh::Parameters = sh::Parameters {
+    a: 0.001_4,
+    b: 0.000_237,
+    c: 0.000_000_099,
+    parallel_r: 5_110.0,  // Ohm (TODO: verify)
+};
+
+// TODO: maybe rename to `TECS`?
+/// Number of TEC channels with four PWM channels each
+pub const CHANNELS: usize = 2;
+
+// TODO: maybe rename to `TecState`?
+/// State per TEC channel
+#[derive(Clone)]
+struct ControlState {
+    /// Report data (time, data, temperature)
+    report: Option<(u64, i32, f32, Option<u16>)>,
+    pid_enabled: bool,
+    pid: pid::Controller,
+    sh: sh::Parameters,
+}
+
+#[cfg(not(test))]
+#[entry]
+fn main() -> ! {
+    let mut stdout = hio::hstdout().unwrap();
+    writeln!(stdout, "tecpak boot").unwrap();
+    board::init();
+    writeln!(stdout, "board initialized").unwrap();
+    let mut tec0 = Tec::tec0().setup(PWM_PID_WIDTH / 2, PWM_PID_WIDTH);
+    let mut tec1 = Tec::tec1().setup(PWM_PID_WIDTH / 2, PWM_PID_WIDTH);
+
+    println!(r#"
+  _                         _
+ | |                       | |
+/  _/___  _ __  _ __   __ _| |
+ | |/ _ \ /'__\| '_ \ / _` | |/ /
+ | | (/_/| |___| |_) | (_| |   <
+ |_|\___\ \___/| .__/ \__,_|_|\_\
+               | |
+               |_|             v1
+"#);
+    // CSn
+    let pb4 = board::gpio::PB4.into_output();
+    // SCLK
+    let pb5 = board::gpio::PB5.into_output();
+    // MOSI
+    let pe4 = board::gpio::PE4.into_output();
+    // MISO
+    let pe5 = board::gpio::PE5.into_input();
+    // max 2 MHz = 0.5 us
+    let mut delay_fn = || for _ in 0..10 { cortex_m::asm::nop(); };
+    let spi = board::softspi::SyncSoftSpi::new(
+        board::softspi::SoftSpi::new(pb5, pe4, pe5),
+        &mut delay_fn
+    );
+    let mut adc = ad7172::Adc::new(spi, pb4).unwrap();
+    loop {
+        let r = adc.identify();
+        match r {
+            Err(e) =>
+                writeln!(stdout, "Cannot identify ADC: {:?}", e).unwrap(),
+            Ok(id) if id & 0xFFF0 == 0x00D0 => {
+                writeln!(stdout, "ADC id: {:04X}", id).unwrap();
+                break;
+            }
+            Ok(_id) => {
+                // This always happens on the first attempt. So retry silently
+            }
+        };
+    }
+    writeln!(stdout, "AD7172: setting checksum mode").unwrap();
+    adc.set_checksum_mode(ad7172::ChecksumMode::Crc).unwrap();
+    loop {
+        let r = adc.identify();
+        match r {
+            Err(e) =>
+                writeln!(stdout, "Cannot identify ADC: {:?}", e).unwrap(),
+            Ok(id) if id & 0xFFF0 == 0x00D0 => {
+                writeln!(stdout, "ADC id: {:04X}", id).unwrap();
+                break;
+            }
+            Ok(id) =>
+                writeln!(stdout, "Corrupt ADC id: {:04X}", id).unwrap(),
+        };
+    }
+    adc.set_sync_enable(false).unwrap();
+    // SENS0_{P,N}
+    adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
+    // SENS1_{P,N}
+    adc.setup_channel(1, ad7172::Input::Ain2, ad7172::Input::Ain3).unwrap();
+
+    let init_state = ControlState {
+        report: None,
+        // Start with disengaged PID to let user setup parameters first
+        pid_enabled: false,
+        pid: pid::Controller::new(DEFAULT_PID_PARAMETERS.clone()),
+        sh: DEFAULT_SH_PARAMETERS.clone(),
+    };
+    let mut states = [init_state.clone(), init_state.clone()];
+
+    let mut hardware_addr = EthernetAddress(board::get_mac_address());
+    writeln!(stdout, "MAC address: {}", hardware_addr).unwrap();
+    if hardware_addr.is_multicast() {
+        writeln!(stdout, "programmed MAC address is invalid, using default").unwrap();
+        hardware_addr = EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]);
+    }
+    let mut ip_addrs = [IpCidr::new(IpAddress::v4(192, 168, 1, 26), 24)];
+    println!("MAC {} IP {}", hardware_addr, ip_addrs[0]);
+    let mut neighbor_cache_storage = [None; 8];
+    let neighbor_cache = NeighborCache::new(&mut neighbor_cache_storage[..]);
+    let mut device = ethmac::Device::new();
+    unsafe { device.init(hardware_addr) };
+    let mut iface = EthernetInterfaceBuilder::new(&mut device)
+                .ethernet_addr(hardware_addr)
+                .neighbor_cache(neighbor_cache)
+                .ip_addrs(&mut ip_addrs[..])
+                .finalize();
+
+    create_socket_storage!(tcp_rx_storage0, tcp_tx_storage0);
+    create_socket_storage!(tcp_rx_storage1, tcp_tx_storage1);
+    create_socket_storage!(tcp_rx_storage2, tcp_tx_storage2);
+    create_socket_storage!(tcp_rx_storage3, tcp_tx_storage3);
+    create_socket_storage!(tcp_rx_storage4, tcp_tx_storage4);
+    create_socket_storage!(tcp_rx_storage5, tcp_tx_storage5);
+    create_socket_storage!(tcp_rx_storage6, tcp_tx_storage6);
+    create_socket_storage!(tcp_rx_storage7, tcp_tx_storage7);
+
+    let mut socket_set_entries: [_; 8] = Default::default();
+    let mut sockets = SocketSet::new(&mut socket_set_entries[..]);
+
+    create_socket!(sockets, tcp_rx_storage0, tcp_tx_storage0, tcp_handle0);
+    create_socket!(sockets, tcp_rx_storage1, tcp_tx_storage1, tcp_handle1);
+    create_socket!(sockets, tcp_rx_storage2, tcp_tx_storage2, tcp_handle2);
+    create_socket!(sockets, tcp_rx_storage3, tcp_tx_storage3, tcp_handle3);
+    create_socket!(sockets, tcp_rx_storage4, tcp_tx_storage4, tcp_handle4);
+    create_socket!(sockets, tcp_rx_storage5, tcp_tx_storage5, tcp_handle5);
+    create_socket!(sockets, tcp_rx_storage6, tcp_tx_storage6, tcp_handle6);
+    create_socket!(sockets, tcp_rx_storage7, tcp_tx_storage7, tcp_handle7);
+    let mut sessions_handles = [
+        (Session::new(), tcp_handle0),
+        (Session::new(), tcp_handle1),
+        (Session::new(), tcp_handle2),
+        (Session::new(), tcp_handle3),
+        (Session::new(), tcp_handle4),
+        (Session::new(), tcp_handle5),
+        (Session::new(), tcp_handle6),
+        (Session::new(), tcp_handle7),
+    ];
+
+    loop {
+        // ADC input
+        adc.data_ready()
+            .unwrap_or_else(|e| {
+                writeln!(stdout, "ADC error: {:?}", e).unwrap();
+                None
+            }).map(|channel| {
+                let now = get_time();
+                let data = adc.read_data().unwrap();
+                let state = &mut states[usize::from(channel)];
+                let voltage = VCC * (data as f32) / (0x7FFFFF as f32);
+                let temperature = state.sh.get_temperature(voltage);
+
+                let pwm_width = if state.pid_enabled {
+                    let width = state.pid.update(temperature) as u16;
+                    match channel {
+                        0 => tec0.set(TecPin::ISet, width, PWM_PID_WIDTH),
+                        1 => tec1.set(TecPin::ISet, width, PWM_PID_WIDTH),
+                        _ => unreachable!(),
+                    }
+                    Some(width)
+                } else {
+                    None
+                };
+
+                state.report = Some((now, data, temperature, pwm_width));
+                for (session, _) in sessions_handles.iter_mut() {
+                    session.set_report_pending(channel.into());
+                }
+            });
+
+        for (session, tcp_handle) in sessions_handles.iter_mut() {
+            let socket = &mut *sockets.get::<TcpSocket>(*tcp_handle);
+            if !socket.is_open() {
+                if session.is_dirty() {
+                    // Reset a previously uses session/socket
+                    *session = Session::new();
+                }
+                socket.listen(23).unwrap()
+            }
+
+            if socket.may_recv() && socket.may_send() {
+                let output = socket.recv(|buf| session.feed(buf));
+
+                // TODO: use "{}" to display pretty errors
+                match output {
+                    Ok(SessionOutput::Nothing) => {}
+                    Ok(SessionOutput::Command(command)) => match command {
+                        Command::Quit =>
+                            socket.close(),
+                        Command::Reporting(reporting) => {
+                            let _ = writeln!(socket, "report={}", if reporting { "on" } else { "off" });
+                        }
+                        Command::Show(ShowCommand::Reporting) => {
+                            let _ = writeln!(socket, "report={}", if session.reporting() { "on" } else { "off" });
+                        }
+                        Command::Show(ShowCommand::Input) => {
+                            for (channel, state) in states.iter().enumerate() {
+                                state.report.map(|(time, data, temp, pwm_width)| {
+                                    let _ = write!(
+                                        socket, "t={} temp{}={} raw{}=0x{:06X}",
+                                        time, channel, temp, channel, data
+                                    );
+                                    pwm_width.map(|width| {
+                                        let _ = write!(
+                                            socket, " pwm{}=0x{:04X}",
+                                            channel, width
+                                        );
+                                    });
+                                    let _ = writeln!(socket, "");
+                                });
+                            }
+                        }
+                        Command::Show(ShowCommand::Pid) => {
+                            for (channel, state) in states.iter().enumerate() {
+                                let _ = writeln!(socket, "PID settings for channel {}", channel);
+                                let pid = &state.pid;
+                                let _ = writeln!(socket, "- target={:.4}", pid.get_target());
+                                let p = pid.get_parameters();
+                                macro_rules! out {
+                                    ($p: tt) => {
+                                        let _ = writeln!(socket, "- {}={:.4}", stringify!($p), p.$p);
+                                    };
+                                }
+                                out!(kp);
+                                out!(ki);
+                                out!(kd);
+                                out!(output_min);
+                                out!(output_max);
+                                out!(integral_min);
+                                out!(integral_max);
+                                let _ = writeln!(socket, "");
+                            }
+                        }
+                        Command::Show(ShowCommand::Pwm) => {
+                            for (channel, state) in states.iter().enumerate() {
+                                let _ = writeln!(
+                                    socket, "channel {}: PID={}",
+                                    channel,
+                                    if state.pid_enabled { "engaged" } else { "disengaged" }
+                                );
+                                for pin in TecPin::VALID_VALUES {
+                                    let (width, total) = match channel {
+                                        0 => tec0.get(*pin),
+                                        1 => tec1.get(*pin),
+                                        _ => unreachable!(),
+                                    };
+                                    let _ = writeln!(socket, "- {}={}/{}", pin, width, total);
+                                }
+                                let _ = writeln!(socket, "");
+                            }
+                        }
+                        Command::Show(ShowCommand::SteinhartHart) => {
+                            for (channel, state) in states.iter().enumerate() {
+                                let _ = writeln!(
+                                    socket, "channel {}: Steinhart-Hart equation parameters",
+                                    channel,
+                                );
+                                let _ = writeln!(socket, "- a={}", state.sh.a);
+                                let _ = writeln!(socket, "- b={}", state.sh.b);
+                                let _ = writeln!(socket, "- c={}", state.sh.c);
+                                let _ = writeln!(socket, "- parallel_r={}", state.sh.parallel_r);
+                                let _ = writeln!(socket, "");
+                            }
+                        }
+                        Command::Show(ShowCommand::PostFilter) => {
+                            for (channel, _) in states.iter().enumerate() {
+                                match adc.get_postfilter(channel as u8).unwrap() {
+                                    Some(filter) => {
+                                        let _ = writeln!(
+                                            socket, "channel {}: postfilter={:.2} SPS",
+                                            channel, filter.output_rate().unwrap()
+                                        );
+                                    }
+                                    None => {
+                                        let _ = writeln!(
+                                            socket, "channel {}: no postfilter",
+                                            channel
+                                        );
+                                    }
+                                }
+                            }
+                        }
+                        Command::Pwm { channel, setup: PwmSetup::ISet(PwmMode::Pid) } => {
+                            states[channel].pid_enabled = true;
+                            let _ = writeln!(socket, "channel {}: PID enabled to control PWM", channel);
+                        }
+                        Command::Pwm { channel, setup: PwmSetup::ISet(PwmMode::Manual(config))} => {
+                            states[channel].pid_enabled = false;
+                            let PwmConfig { width, total } = config;
+                            match channel {
+                                0 => tec0.set(TecPin::ISet, width, total),
+                                1 => tec1.set(TecPin::ISet, width, total),
+                                _ => unreachable!(),
+                            }
+                            let _ = writeln!(
+                                socket, "channel {}: PWM duty cycle manually set to {}/{}",
+                                channel, config.width, config.total
+                            );
+                        }
+                        Command::Pwm { channel, setup } => {
+                            let (pin, config) = match setup {
+                                PwmSetup::ISet(_) =>
+                                    // Handled above
+                                    unreachable!(),
+                                PwmSetup::MaxIPos(config) =>
+                                    (TecPin::MaxIPos, config),
+                                PwmSetup::MaxINeg(config) =>
+                                    (TecPin::MaxINeg, config),
+                                PwmSetup::MaxV(config) =>
+                                    (TecPin::MaxV, config),
+                            };
+                            let PwmConfig { width, total } = config;
+                            match channel {
+                                0 => tec0.set(pin, width, total),
+                                1 => tec1.set(pin, width, total),
+                                _ => unreachable!(),
+                            }
+                            let _ = writeln!(
+                                socket, "channel {}: PWM {} reconfigured to {}/{}",
+                                channel, pin, width, total
+                            );
+                        }
+                        Command::Pid { channel, parameter, value } => {
+                            let pid = &mut states[channel].pid;
+                            use command_parser::PidParameter::*;
+                            match parameter {
+                                Target =>
+                                    pid.set_target(value),
+                                KP =>
+                                    pid.update_parameters(|parameters| parameters.kp = value),
+                                KI =>
+                                    pid.update_parameters(|parameters| parameters.ki = value),
+                                KD =>
+                                    pid.update_parameters(|parameters| parameters.kd = value),
+                                OutputMin =>
+                                    pid.update_parameters(|parameters| parameters.output_min = value),
+                                OutputMax =>
+                                    pid.update_parameters(|parameters| parameters.output_max = value),
+                                IntegralMin =>
+                                    pid.update_parameters(|parameters| parameters.integral_min = value),
+                                IntegralMax =>
+                                    pid.update_parameters(|parameters| parameters.integral_max = value),
+                            }
+                            pid.reset();
+                            let _ = writeln!(socket, "PID parameter updated");
+                        }
+                        Command::SteinhartHart { channel, parameter, value } => {
+                            let sh = &mut states[channel].sh;
+                            use command_parser::ShParameter::*;
+                            match parameter {
+                                A => sh.a = value,
+                                B => sh.b = value,
+                                C => sh.c = value,
+                                ParallelR => sh.parallel_r = value,
+                            }
+                            let _ = writeln!(socket, "Steinhart-Hart equation parameter updated");
+                        }
+                        Command::PostFilter { channel, rate } => {
+                            let filter = ad7172::PostFilter::closest(rate);
+                            match filter {
+                                Some(filter) => {
+                                    adc.set_postfilter(channel as u8, Some(filter)).unwrap();
+                                    let _ = writeln!(
+                                        socket, "channel {}: postfilter set to {:.2} SPS",
+                                        channel, filter.output_rate().unwrap()
+                                    );
+                                }
+                                None => {
+                                    let _ = writeln!(socket, "Unable to choose postfilter");
+                                }
+                            }
+                        }
+                    }
+                    Ok(SessionOutput::Error(e)) => {
+                        let _ = writeln!(socket, "Command error: {:?}", e);
+                    }
+                    Err(_) => {}
+                }
+            }
+            if socket.may_send() {
+                if let Some(channel) = session.is_report_pending() {
+                    states[channel].report.map(|(time, data, temp, pwm_width)| {
+                        let _ = write!(
+                            socket, "t={} temp{}={} raw{}=0x{:06X}",
+                            time, channel, temp, channel, data
+                        );
+                        pwm_width.map(|width| {
+                            let _ = write!(
+                                socket, " pwm{}=0x{:04X}",
+                                channel, width
+                            );
+                        });
+                        let _ = writeln!(socket, "");
+                    });
+                    session.mark_report_sent(channel);
+                }
+            }
+        }
+        match iface.poll(&mut sockets, Instant::from_millis((get_time() / 1000) as i64)) {
+            Ok(_) => (),
+            Err(e) => println!("poll error: {}", e)
+        }
+    }
+}
--- a/firmware/src/pid.rs
+++ b/firmware/src/pid.rs
@ -0,0 +1,122 @@
+#[derive(Clone, Copy)]
+pub struct Parameters {
+    pub kp: f32,
+    pub ki: f32,
+    pub kd: f32,
+    pub output_min: f32,
+    pub output_max: f32,
+    pub integral_min: f32,
+    pub integral_max: f32
+}
+
+#[derive(Clone)]
+pub struct Controller {
+    parameters: Parameters,
+    target: f32,
+    integral: f32,
+    last_input: Option<f32>
+}
+
+impl Controller {
+    pub const fn new(parameters: Parameters) -> Controller {
+        Controller {
+            parameters: parameters,
+            target: 0.0,
+            last_input: None,
+            integral: 0.0
+        }
+    }
+
+    pub fn update(&mut self, input: f32) -> f32 {
+        let error = self.target - input;
+
+        let p = self.parameters.kp * error;
+
+        self.integral += error;
+        if self.integral < self.parameters.integral_min {
+            self.integral = self.parameters.integral_min;
+        }
+        if self.integral > self.parameters.integral_max {
+            self.integral = self.parameters.integral_max;
+        }
+        let i = self.parameters.ki * self.integral;
+
+        let d = match self.last_input {
+            None => 0.0,
+            Some(last_input) => self.parameters.kd * (last_input - input)
+        };
+        self.last_input = Some(input);
+
+        let mut output = p + i + d;
+        if output < self.parameters.output_min {
+            output = self.parameters.output_min;
+        }
+        if output > self.parameters.output_max {
+            output = self.parameters.output_max;
+        }
+        output
+    }
+
+    pub fn get_target(&self) -> f32 {
+        self.target
+    }
+
+    pub fn set_target(&mut self, target: f32) {
+        self.target = target;
+    }
+
+    pub fn get_parameters(&self) -> &Parameters {
+        &self.parameters
+    }
+
+    pub fn update_parameters<F: FnOnce(&mut Parameters)>(&mut self, f: F) {
+        f(&mut self.parameters);
+    }
+
+    #[allow(dead_code)]
+    pub fn reset(&mut self) {
+        self.integral = 0.0;
+        self.last_input = None;
+    }
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    const PARAMETERS: Parameters = Parameters {
+        kp: 0.055,
+        ki: 0.005,
+        kd: 0.04,
+        output_min: -10.0,
+        output_max: 10.0,
+        integral_min: -100.0,
+        integral_max: 100.0,
+    };
+
+    #[test]
+    fn test_controller() {
+        const DEFAULT: f32 = 0.0;
+        const TARGET: f32 = 1234.56;
+        const ERROR: f32 = 0.01;
+        const DELAY: usize = 10;
+
+        let mut pid = Controller::new(PARAMETERS.clone());
+        pid.set_target(TARGET);
+
+        let mut values = [DEFAULT; DELAY];
+        let mut t = 0;
+        let mut total_t = 0;
+        let target = (TARGET - ERROR)..=(TARGET + ERROR);
+        while !values.iter().all(|value| target.contains(value)) {
+            let next_t = (t + 1) % DELAY;
+            // Feed the oldest temperature
+            let output = pid.update(values[next_t]);
+            // Overwrite oldest with previous temperature + output
+            values[next_t] = values[t] + output;
+            t = next_t;
+            total_t += 1;
+        }
+        dbg!(values[t], total_t);
+    }
+}
--- a/firmware/src/session.rs
+++ b/firmware/src/session.rs
@ -0,0 +1,138 @@
+use core::ops::Deref;
+use super::command_parser::{Command, Error as ParserError};
+use super::CHANNELS;
+
+const MAX_LINE_LEN: usize = 64;
+
+struct LineReader {
+    buf: [u8; MAX_LINE_LEN],
+    pos: usize,
+}
+
+impl LineReader {
+    pub fn new() -> Self {
+        LineReader {
+            buf: [0; MAX_LINE_LEN],
+            pos: 0,
+        }
+    }
+
+    pub fn feed(&mut self, c: u8) -> Option<LineResult> {
+        if c == 13 || c == 10 {
+            // Enter
+            if self.pos > 0 {
+                let len = self.pos;
+                self.pos = 0;
+                Some(LineResult {
+                    buf: self.buf.clone(),
+                    len,
+                })
+            } else {
+                None
+            }
+        } else if self.pos < self.buf.len() {
+            // Add input
+            self.buf[self.pos] = c;
+            self.pos += 1;
+            None
+        } else {
+            // Buffer is full, ignore
+            None
+        }
+    }
+}
+
+pub struct LineResult {
+    buf: [u8; MAX_LINE_LEN],
+    len: usize,
+}
+
+impl Deref for LineResult {
+    type Target = [u8];
+    fn deref(&self) -> &Self::Target {
+        &self.buf[..self.len]
+    }
+}
+
+pub enum SessionOutput {
+    Nothing,
+    Command(Command),
+    Error(ParserError),
+}
+
+impl From<Result<Command, ParserError>> for SessionOutput {
+    fn from(input: Result<Command, ParserError>) -> Self {
+        input.map(SessionOutput::Command)
+            .unwrap_or_else(SessionOutput::Error)
+    }
+}
+
+pub struct Session {
+    reader: LineReader,
+    reporting: bool,
+    report_pending: [bool; CHANNELS],
+}
+
+impl Session {
+    pub fn new() -> Self {
+        Session {
+            reader: LineReader::new(),
+            reporting: false,
+            report_pending: [false; CHANNELS],
+        }
+    }
+
+    pub fn is_dirty(&self) -> bool {
+        self.reader.pos > 0
+    }
+
+    pub fn reporting(&self) -> bool {
+        self.reporting
+    }
+
+    pub fn set_report_pending(&mut self, channel: usize) {
+        if self.reporting {
+            self.report_pending[channel] = true;
+        }
+    }
+
+    pub fn is_report_pending(&self) -> Option<usize> {
+        if ! self.reporting {
+            None
+        } else {
+            self.report_pending.iter()
+                .enumerate()
+                .fold(None, |result, (channel, report_pending)| {
+                    result.or_else(|| {
+                        if *report_pending { Some(channel) } else { None }
+                    })
+                })
+        }
+    }
+
+    pub fn mark_report_sent(&mut self, channel: usize) {
+        self.report_pending[channel] = false;
+    }
+
+    pub fn feed(&mut self, buf: &[u8]) -> (usize, SessionOutput) {
+        let mut buf_bytes = 0;
+        for (i, b) in buf.iter().enumerate() {
+            buf_bytes = i + 1;
+            let line = self.reader.feed(*b);
+            match line {
+                Some(line) => {
+                    let command = Command::parse(&line);
+                    match command {
+                        Ok(Command::Reporting(reporting)) => {
+                            self.reporting = reporting;
+                        }
+                        _ => {}
+                    }
+                    return (buf_bytes, command.into());
+                }
+                None => {}
+            }
+        }
+        (buf_bytes, SessionOutput::Nothing)
+    }
+}
--- a/firmware/src/steinhart_hart.rs
+++ b/firmware/src/steinhart_hart.rs
@ -0,0 +1,30 @@
+use libm::F32Ext;
+
+/// Steinhart-Hart equation parameters
+#[derive(Clone, Debug)]
+pub struct Parameters {
+    pub a: f32,
+    pub b: f32,
+    pub c: f32,
+    /// Parallel resistance
+    ///
+    /// Not truly part of the equation but required to calculate
+    /// resistance from voltage.
+    pub parallel_r: f32,
+}
+
+impl Parameters {
+    /// Perform the voltage to temperature conversion.
+    ///
+    /// Result unit: Kelvin
+    ///
+    /// TODO: verify
+    pub fn get_temperature(&self, voltage: f32) -> f32 {
+        let r = self.parallel_r * voltage;
+        let ln_r = r.abs().ln();
+        let inv_temp = self.a +
+            self.b * ln_r +
+            self.c * ln_r * ln_r * ln_r;
+        1.0 / inv_temp
+    }
+}
--- a/firmware/src/style.css.gz
+++ b/firmware/src/style.css.gz
--- a/firmware/src/tec.rs
+++ b/firmware/src/tec.rs
@ -0,0 +1,128 @@
+use core::fmt;
+use crate::board::pwm::{self, PwmChannel, PwmPeripheral};
+use crate::board::gpio::{Gpio, GpioOutput, PP2, PP3, PK1, PQ4};
+use embedded_hal::digital::v2::OutputPin;
+
+#[derive(Clone, Copy, Debug)]
+pub enum TecPin {
+    ISet,
+    MaxIPos,
+    MaxINeg,
+    MaxV,
+}
+
+impl TecPin {
+    pub const VALID_VALUES: &'static [TecPin] = &[
+        TecPin::ISet,
+        TecPin::MaxIPos,
+        TecPin::MaxINeg,
+        TecPin::MaxV,
+    ];
+}
+
+impl fmt::Display for TecPin {
+    fn fmt(&self, fmt: &mut fmt::Formatter) -> Result<(), fmt::Error> {
+        match self {
+            TecPin::ISet =>
+                "i_set".fmt(fmt),
+            TecPin::MaxIPos =>
+                "max_i_pos".fmt(fmt),
+            TecPin::MaxINeg =>
+                "max_i_neg".fmt(fmt),
+            TecPin::MaxV =>
+                "max_v".fmt(fmt),
+        }
+    }
+}
+
+fn setup_shdn<G>(gpio: G) -> GpioOutput<G>
+where
+    G: Gpio,
+    GpioOutput<G>: OutputPin,
+{
+    let mut pin = gpio.into_output();
+    // keep off until first use
+    let _ = pin.set_low();
+    pin
+}
+
+fn setup_freq<G>(gpio: G)
+where
+    G: Gpio,
+    GpioOutput<G>: OutputPin,
+{
+    let mut pin = gpio.into_output();
+    // Switching Frequency Select
+    // high: 1 MHz, low: 500 kHz
+    let _ = pin.set_high();
+}
+
+/// Thermo-Electric Cooling device controlled through four PWM
+/// channels
+pub struct Tec<MaxIPos: PwmChannel, MaxINeg: PwmChannel, ISet: PwmChannel, MaxV: PwmChannel, SHDN: OutputPin> {
+    max_i_pos: MaxIPos,
+    max_i_neg: MaxINeg,
+    i_set: ISet,
+    max_v: MaxV,
+    shdn: SHDN,
+}
+
+impl Tec<pwm::T2CCP0, pwm::T2CCP1, pwm::T3CCP0, pwm::T3CCP1, GpioOutput<PP2>> {
+    pub fn tec0() -> Self {
+        let (max_i_pos, max_i_neg) = tm4c129x::TIMER2::split();
+        let (i_set, max_v) = tm4c129x::TIMER3::split();
+        let shdn = setup_shdn(PP2);
+        setup_freq(PK1);
+        Tec { max_i_pos, max_i_neg, i_set, max_v, shdn }
+    }
+}
+
+impl Tec<pwm::T4CCP0, pwm::T4CCP1, pwm::T5CCP0, pwm::T5CCP1, GpioOutput<PP3>> {
+    pub fn tec1() -> Self {
+        let (max_i_pos, max_i_neg) = tm4c129x::TIMER4::split();
+        let (i_set, max_v) = tm4c129x::TIMER5::split();
+        let shdn = setup_shdn(PP3);
+        setup_freq(PQ4);
+        Tec { max_i_pos, max_i_neg, i_set, max_v, shdn }
+    }
+}
+
+
+impl<MaxIPos: PwmChannel, MaxINeg: PwmChannel, ISet: PwmChannel, MaxV: PwmChannel, SHDN: OutputPin> Tec<MaxIPos, MaxINeg, ISet, MaxV, SHDN> {
+    pub fn setup(mut self, iset_width: u16, max: u16) -> Self {
+        self.max_i_pos.set(max, max);
+        self.max_i_neg.set(max, max);
+        self.max_v.set(max, max);
+        self.i_set.set(iset_width, max);
+        self
+    }
+
+    pub fn get(&mut self, pin: TecPin) -> (u16, u16) {
+        match pin {
+            TecPin::MaxIPos =>
+                self.max_i_pos.get(),
+            TecPin::MaxINeg =>
+                self.max_i_neg.get(),
+            TecPin::ISet =>
+                self.i_set.get(),
+            TecPin::MaxV =>
+                self.max_v.get(),
+        }
+    }
+
+    pub fn set(&mut self, pin: TecPin, width: u16, total: u16) {
+        match pin {
+            TecPin::MaxIPos =>
+                self.max_i_pos.set(width, total),
+            TecPin::MaxINeg =>
+                self.max_i_neg.set(width, total),
+            TecPin::ISet => {
+                self.i_set.set(width, total);
+                // enable on first use
+                let _ = self.shdn.set_high();
+            }
+            TecPin::MaxV =>
+                self.max_v.set(width, total),
+        }
+    }
+}
--- a/proto_rev1.jpg
+++ b/proto_rev1.jpg
--- a/proto_rev1_resized.jpg
+++ b/proto_rev1_resized.jpg
--- a/shell.nix
+++ b/shell.nix
@ -0,0 +1,28 @@
+let
+  mozillaOverlay = import (builtins.fetchTarball https://github.com/mozilla/nixpkgs-mozilla/archive/master.tar.gz);
+  pkgs = import <nixpkgs> { overlays = [ mozillaOverlay ]; };
+in
+with pkgs;
+let
+  project = callPackage ./default.nix {};
+in
+with project;
+stdenv.mkDerivation {
+  name = "armdev-env";
+  buildInputs = with rustPlatform.rust; [
+    rustc cargo cargo-xbuild
+    rustcSrc
+    pkgsCross.arm-embedded.stdenv.cc
+    openocd
+  ];
+
+  # Set Environment Variables
+  RUST_BACKTRACE = 1;
+  XARGO_RUST_SRC = "${rustcSrc}/src";
+  RUST_COMPILER_RT_ROOT = "${rustcSrc}/src/llvm-project/compiler-rt";
+
+  shellHook = ''
+    cd firmware
+    echo "Run 'cargo xbuild --release' to build."
+  '';
+}