M-Labs
/
ionpak-thermostat
7
0
Fork 1
Code Issues Pull Requests Releases Wiki Activity

Enable PLL at 320 MHz.

pull/1/head
whitequark 2017-05-07 16:28:03 +00:00
parent 8353ffbe98
commit 0ba8971aff
2 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
firmware/Cargo.lock generated
View File

@ -43,7 +43,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
[[package]]
name = "tm4c129x"
version = "0.4.0"
source = "git+https://github.com/m-labs/dslite2svd#f1b9a75e478c2186bf963ae1f868109fd14def29"
source = "git+https://github.com/m-labs/dslite2svd#43d3964bb9dcebe631b0bdf1c2fdc975cf53c41c"
dependencies = [
"cortex-m 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)",
"vcell 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)",

10
firmware/src/main.rs
View File

@ -126,6 +126,16 @@ fn main() {
let sysctl = tm4c129x::SYSCTL.borrow(cs);
let nvic = tm4c129x::NVIC.borrow(cs);
// Set up main oscillator
sysctl.moscctl.write(|w| w.noxtal().bit(false));
sysctl.moscctl.modify(|_, w| w.pwrdn().bit(false).oscrng().bit(true));
// Set up PLL with fVCO=320 MHz
sysctl.pllfreq1.write(|w| w.q().bits(0).n().bits(4));
sysctl.pllfreq0.write(|w| w.mint().bits(64).pllpwr().bit(true));
sysctl.rsclkcfg.modify(|_, w| w.pllsrc().mosc().newfreq().bit(true));
while !sysctl.pllstat.read().lock().bit() {}
// Set up system timer
let systick = tm4c129x::SYST.borrow(cs);
systick.set_reload(systick.get_ticks_per_10ms());