448 lines
15 KiB
Rust
448 lines
15 KiB
Rust
use core::{slice, cmp};
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use cortex_m::{self, asm::delay};
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use tm4c129x;
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use smoltcp::Result;
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use smoltcp::time::Instant;
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use smoltcp::wire::EthernetAddress;
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use smoltcp::phy;
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const EPHY_BMCR: u8 = 0x00; // Ethernet PHY Basic Mode Control
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#[allow(dead_code)]
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const EPHY_BMSR: u8 = 0x01; // Ethernet PHY Basic Mode Status
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const EPHY_ID1: u8 = 0x02; // Ethernet PHY Identifier Register 1
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const EPHY_ID2: u8 = 0x03; // Ethernet PHY Identifier Register 2
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const EPHY_REGCTL: u8 = 0x0D; // Ethernet PHY Register Control
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const EPHY_ADDAR: u8 = 0x0E; // Ethernet PHY Address or Data
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const EPHY_LEDCFG: u8 = 0x25; // Ethernet PHY LED Configuration
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// Transmit DMA descriptor flags
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const EMAC_TDES0_OWN: u32 = 0x80000000; // Indicates that the descriptor is owned by the DMA
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const EMAC_TDES0_LS: u32 = 0x20000000; // Last Segment
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const EMAC_TDES0_FS: u32 = 0x10000000; // First Segment
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const EMAC_TDES0_TCH: u32 = 0x00100000; // Second Address Chained
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#[allow(dead_code)]
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const EMAC_TDES1_TBS1: u32 = 0x00001FFF; // Transmit Buffer 1 Size
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// Receive DMA descriptor flags
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const EMAC_RDES0_OWN: u32 = 0x80000000; // indicates that the descriptor is owned by the DMA
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const EMAC_RDES0_FL: u32 = 0x3FFF0000; // Frame Length
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const EMAC_RDES0_ES: u32 = 0x00008000; // Error Summary
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const EMAC_RDES0_FS: u32 = 0x00000200; // First Descriptor
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const EMAC_RDES0_LS: u32 = 0x00000100; // Last Descriptor
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const EMAC_RDES1_RCH: u32 = 0x00004000; // Second Address Chained
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const EMAC_RDES1_RBS1: u32 = 0x00001FFF; // Receive Buffer 1 Size
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const ETH_DESC_U32_SIZE: usize = 8;
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const ETH_TX_BUFFER_COUNT: usize = 2;
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const ETH_TX_BUFFER_SIZE: usize = 1536;
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const ETH_RX_BUFFER_COUNT: usize = 3;
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const ETH_RX_BUFFER_SIZE: usize = 1536;
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fn phy_read(reg_addr: u8) -> u16 {
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cortex_m::interrupt::free(|_cs| {
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let emac0 = unsafe { &*tm4c129x::EMAC0::ptr() };
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// Make sure the MII is idle
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while emac0.miiaddr.read().miib().bit() {};
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// Tell the MAC to read the given PHY register
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unsafe {
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emac0.miiaddr.write(|w| {
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w.cr()._100_150()
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.mii().bits(reg_addr & 0x1F)
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.miib().bit(true)
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});
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}
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// Wait for the read to complete
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while emac0.miiaddr.read().miib().bit() {};
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emac0.miidata.read().data().bits()
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})
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}
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fn phy_write(reg_addr: u8, reg_data: u16) {
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cortex_m::interrupt::free(|_cs| {
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let emac0 = unsafe { &*tm4c129x::EMAC0::ptr() };
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// Make sure the MII is idle
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while emac0.miiaddr.read().miib().bit() {};
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unsafe {
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emac0.miidata.write(|w| {
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w.data().bits(reg_data)
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});
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// Tell the MAC to write the given PHY register
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emac0.miiaddr.write(|w| {
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w.cr()._100_150()
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.mii().bits(reg_addr & 0x1F)
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.miiw().bit(true)
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.miib().bit(true)
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});
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}
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// Wait for the read to complete
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while emac0.miiaddr.read().miib().bit() {};
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})
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}
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// Writes a value to an extended PHY register in MMD address space
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fn phy_write_ext(reg_addr: u8, reg_data: u16) {
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phy_write(EPHY_REGCTL, 0x001F); // set address (datasheet page 1612)
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phy_write(EPHY_ADDAR, reg_addr as u16);
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phy_write(EPHY_REGCTL, 0x401F); // set write mode
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phy_write(EPHY_ADDAR, reg_data);
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}
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struct RxRing {
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desc_buf: [u32; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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cur_desc: usize,
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counter: u32,
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pkt_buf: [u8; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
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}
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impl RxRing {
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fn new() -> RxRing {
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RxRing {
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desc_buf: [0; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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cur_desc: 0,
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counter: 0,
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pkt_buf: [0; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
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}
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}
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fn init(&mut self) {
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// Initialize RX DMA descriptors
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for x in 0..ETH_RX_BUFFER_COUNT {
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let p = x * ETH_DESC_U32_SIZE;
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let r = x * ETH_RX_BUFFER_SIZE;
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// The descriptor is initially owned by the DMA
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self.desc_buf[p + 0] = EMAC_RDES0_OWN;
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// Use chain structure rather than ring structure
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self.desc_buf[p + 1] =
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EMAC_RDES1_RCH | ((ETH_RX_BUFFER_SIZE as u32) & EMAC_RDES1_RBS1);
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// Receive buffer address
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self.desc_buf[p + 2] = (&self.pkt_buf[r] as *const u8) as u32;
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// Next descriptor address
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if x != ETH_RX_BUFFER_COUNT - 1 {
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self.desc_buf[p + 3] =
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(&self.desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
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} else {
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self.desc_buf[p + 3] =
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(&self.desc_buf[0] as *const u32) as u32;
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}
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// Extended status
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self.desc_buf[p + 4] = 0;
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// Reserved field
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self.desc_buf[p + 5] = 0;
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// Transmit frame time stamp
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self.desc_buf[p + 6] = 0;
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self.desc_buf[p + 7] = 0;
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}
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}
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fn buf_owned(&self) -> bool {
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self.desc_buf[self.cur_desc + 0] & EMAC_RDES0_OWN == 0
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}
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fn buf_valid(&self) -> bool {
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self.desc_buf[self.cur_desc + 0] &
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(EMAC_RDES0_FS | EMAC_RDES0_LS | EMAC_RDES0_ES) ==
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(EMAC_RDES0_FS | EMAC_RDES0_LS)
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}
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unsafe fn buf_as_slice<'a>(&self) -> &'a mut [u8] {
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let len = (self.desc_buf[self.cur_desc + 0] & EMAC_RDES0_FL) >> 16;
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let len = cmp::min(len as usize, ETH_RX_BUFFER_SIZE);
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let addr = self.desc_buf[self.cur_desc + 2] as *mut u8;
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slice::from_raw_parts_mut(addr, len)
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}
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fn buf_release(&mut self) {
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self.cur_desc += ETH_DESC_U32_SIZE;
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if self.cur_desc == self.desc_buf.len() {
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self.cur_desc = 0;
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}
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self.counter += 1;
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self.desc_buf[self.cur_desc + 0] = EMAC_RDES0_OWN;
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}
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}
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struct TxRing {
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desc_buf: [u32; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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cur_desc: usize,
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counter: u32,
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pkt_buf: [u8; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
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}
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impl TxRing {
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fn new() -> TxRing {
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TxRing {
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desc_buf: [0; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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cur_desc: 0,
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counter: 0,
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pkt_buf: [0; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
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}
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}
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fn init(&mut self) {
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// Initialize TX DMA descriptors
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for x in 0..ETH_TX_BUFFER_COUNT {
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let p = x * ETH_DESC_U32_SIZE;
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let r = x * ETH_TX_BUFFER_SIZE;
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// Initialize transmit flags
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self.desc_buf[p + 0] = 0;
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// Initialize transmit buffer size
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self.desc_buf[p + 1] = 0;
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// Transmit buffer address
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self.desc_buf[p + 2] = (&self.pkt_buf[r] as *const u8) as u32;
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// Next descriptor address
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if x != ETH_TX_BUFFER_COUNT - 1 {
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self.desc_buf[p + 3] =
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(&self.desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
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} else {
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self.desc_buf[p + 3] =
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(&self.desc_buf[0] as *const u32) as u32;
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}
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// Reserved fields
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self.desc_buf[p + 4] = 0;
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self.desc_buf[p + 5] = 0;
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// Transmit frame time stamp
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self.desc_buf[p + 6] = 0;
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self.desc_buf[p + 7] = 0;
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}
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}
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fn buf_owned(&self) -> bool {
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self.desc_buf[self.cur_desc + 0] & EMAC_TDES0_OWN == 0
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}
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unsafe fn buf_as_slice<'a>(&mut self, len: usize) -> &'a mut [u8] {
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let len = cmp::min(len, ETH_TX_BUFFER_SIZE);
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self.desc_buf[self.cur_desc + 1] = len as u32;
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let addr = self.desc_buf[self.cur_desc + 2] as *mut u8;
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slice::from_raw_parts_mut(addr, len)
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}
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fn buf_release(&mut self) {
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self.desc_buf[self.cur_desc + 0] =
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EMAC_TDES0_OWN | EMAC_TDES0_LS | EMAC_TDES0_FS | EMAC_TDES0_TCH;
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cortex_m::interrupt::free(|_cs| {
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let emac0 = unsafe { &*tm4c129x::EMAC0::ptr() };
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// Clear TU flag to resume processing
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emac0.dmaris.write(|w| w.tu().bit(true));
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// Instruct the DMA to poll the transmit descriptor list
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unsafe { emac0.txpolld.write(|w| w.tpd().bits(0)); }
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});
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self.cur_desc += ETH_DESC_U32_SIZE;
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if self.cur_desc == self.desc_buf.len() {
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self.cur_desc = 0;
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}
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self.counter += 1;
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}
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}
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pub struct Device {
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rx: RxRing,
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tx: TxRing,
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}
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impl Device {
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pub fn new() -> Device {
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Device {
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rx: RxRing::new(),
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tx: TxRing::new(),
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}
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}
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// After `init` is called, `Device` shall not be moved.
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pub unsafe fn init(&mut self, mac: EthernetAddress) {
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self.rx.init();
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self.tx.init();
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cortex_m::interrupt::free(|_cs| {
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let sysctl = &*tm4c129x::SYSCTL::ptr();
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let emac0 = &*tm4c129x::EMAC0::ptr();
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sysctl.rcgcemac.modify(|_, w| w.r0().bit(true)); // Bring up MAC
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sysctl.sremac.modify(|_, w| w.r0().bit(true)); // Activate MAC reset
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delay(16);
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sysctl.sremac.modify(|_, w| w.r0().bit(false)); // Dectivate MAC reset
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sysctl.rcgcephy.modify(|_, w| w.r0().bit(true)); // Bring up PHY
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sysctl.srephy.modify(|_, w| w.r0().bit(true)); // Activate PHY reset
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delay(16);
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sysctl.srephy.modify(|_, w| w.r0().bit(false)); // Dectivate PHY reset
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while !sysctl.premac.read().r0().bit() {} // Wait for the MAC to come out of reset
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while !sysctl.prephy.read().r0().bit() {} // Wait for the PHY to come out of reset
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delay(10000);
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emac0.dmabusmod.modify(|_, w| w.swr().bit(true)); // Reset MAC DMA
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while emac0.dmabusmod.read().swr().bit() {} // Wait for the MAC DMA to come out of reset
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delay(1000);
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emac0.miiaddr.write(|w| w.cr()._100_150()); // Set the MII CSR clock speed.
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// Checking PHY
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if (phy_read(EPHY_ID1) != 0x2000) | (phy_read(EPHY_ID2) != 0xA221) {
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panic!("PHY ID error!");
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}
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// Reset PHY transceiver
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phy_write(EPHY_BMCR, 1); // Initiate MII reset
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while (phy_read(EPHY_BMCR) & 1) == 1 {}; // Wait for the reset to be completed
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// Configure PHY LEDs
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phy_write_ext(EPHY_LEDCFG, 0x0008); // LED0 Link OK/Blink on TX/RX Activity
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// Tell the PHY to start an auto-negotiation cycle
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phy_write(EPHY_BMCR, 0b00010010_00000000); // ANEN and RESTARTAN
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// Set the DMA operation mode
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emac0.dmaopmode.write(|w|
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w.rsf().bit(true) // Receive Store and Forward
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.tsf().bit(true) // Transmit Store and Forward
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.ttc()._64() // Transmit Threshold Control
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.rtc()._64() // Receive Threshold Control
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);
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// Set the bus mode register.
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emac0.dmabusmod.write(|w|
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w.atds().bit(true)
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.aal().bit(true) // Address Aligned Beats
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.usp().bit(true) // Use Separate Programmable Burst Length ???
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.rpbl().bits(1) // RX DMA Programmable Burst Length
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.pbl().bits(1) // Programmable Burst Length
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.pr().bits(0) // Priority Ratio 1:1
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);
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// Disable all the MMC interrupts as these are enabled by default at reset.
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emac0.mmcrxim.write(|w| w.bits(0xFFFFFFFF));
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emac0.mmctxim.write(|w| w.bits(0xFFFFFFFF));
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// Set MAC configuration options
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emac0.cfg.write(|w|
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w.dupm().bit(true) // MAC operates in full-duplex mode
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.ipc().bit(true) // Checksum Offload Enable
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.prelen()._7() // 7 bytes of preamble
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.ifg()._96() // 96 bit times
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.bl()._1024() // Back-Off Limit 1024
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.ps().bit(true) // ?
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);
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// Set the maximum receive frame size
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emac0.wdogto.write(|w|
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w.bits(0) // ??? no use watchdog
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);
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// Set the MAC address
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emac0.addr0l.write(|w|
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w.addrlo().bits( mac.0[0] as u32 |
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((mac.0[1] as u32) << 8) |
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((mac.0[2] as u32) << 16) |
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((mac.0[3] as u32) << 24))
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);
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emac0.addr0h.write(|w|
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w.addrhi().bits( mac.0[4] as u16 |
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((mac.0[5] as u16) << 8))
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);
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// Set MAC filtering options (?)
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emac0.framefltr.write(|w|
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w.hpf().bit(true) // Hash or Perfect Filter
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//.hmc().bit(true) // Hash Multicast ???
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.pm().bit(true) // Pass All Multicast
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);
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// Initialize hash table
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emac0.hashtbll.write(|w| w.htl().bits(0));
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emac0.hashtblh.write(|w| w.hth().bits(0));
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emac0.flowctl.write(|w| w.bits(0)); // Disable flow control ???
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emac0.txdladdr.write(|w| /*unsafe*/ {
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w.bits((&mut self.tx.desc_buf[0] as *mut u32) as u32)
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});
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emac0.rxdladdr.write(|w| /*unsafe*/ {
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w.bits((&mut self.rx.desc_buf[0] as *mut u32) as u32)
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});
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// Manage MAC transmission and reception
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emac0.cfg.modify(|_, w|
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w.re().bit(true) // Receiver Enable
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.te().bit(true) // Transmiter Enable
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);
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// Manage DMA transmission and reception
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emac0.dmaopmode.modify(|_, w|
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w.sr().bit(true) // Start Receive
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.st().bit(true) // Start Transmit
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);
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});
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}
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}
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impl<'a, 'b> phy::Device<'a> for &'b mut Device {
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type RxToken = RxToken<'a>;
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type TxToken = TxToken<'a>;
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fn capabilities(&self) -> phy::DeviceCapabilities {
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let mut capabilities = phy::DeviceCapabilities::default();
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capabilities.max_transmission_unit = 1500;
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capabilities.max_burst_size = Some(ETH_RX_BUFFER_COUNT);
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capabilities
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}
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fn receive(&mut self) -> Option<(RxToken, TxToken)> {
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// Skip all queued packets with errors.
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while self.rx.buf_owned() && !self.rx.buf_valid() {
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self.rx.buf_release()
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}
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if !(self.rx.buf_owned() && self.tx.buf_owned()) {
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return None
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}
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Some((RxToken(&mut self.rx), TxToken(&mut self.tx)))
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}
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fn transmit(&mut self) -> Option<TxToken> {
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if !self.tx.buf_owned() {
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return None
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}
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Some(TxToken(&mut self.tx))
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}
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}
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pub struct RxToken<'a>(&'a mut RxRing);
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impl<'a> phy::RxToken for RxToken<'a> {
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fn consume<R, F>(self, _timestamp: Instant, f: F) -> Result<R>
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where F: FnOnce(&mut [u8]) -> Result<R> {
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let result = f(unsafe { self.0.buf_as_slice() });
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self.0.buf_release();
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result
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}
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}
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pub struct TxToken<'a>(&'a mut TxRing);
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impl<'a> phy::TxToken for TxToken<'a> {
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fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> Result<R>
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where F: FnOnce(&mut [u8]) -> Result<R> {
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let result = f(unsafe { self.0.buf_as_slice(len) });
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self.0.buf_release();
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result
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}
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}
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