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ionpak-thermostat
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cleanup and integrate EEPROM driver

pull/1/head
Sebastien Bourdeauducq 2017-08-07 16:13:29 +08:00
parent f94b50e9ab
commit d812932732
4 changed files with 49 additions and 82 deletions
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10
firmware/src/board.rs
View File

@ -338,3 +338,13 @@ pub fn get_mac_address() -> [u8; 6] {
[userreg0 as u8, (userreg0 >> 8) as u8, (userreg0 >> 16) as u8,
userreg1 as u8, (userreg1 >> 8) as u8, (userreg1 >> 16) as u8]
}
pub fn delay(d: u32) {
for _ in 0..d {
unsafe {
asm!("
NOP
");
}
}
}

97
firmware/src/eeprom.rs
View File

@ -1,55 +1,37 @@
use core::fmt;
use cortex_m;
use tm4c129x;
use ethmac::delay;
use board;
const EEPROM_BLK_COUNT: u16 = 96; // Number of the blocks
const EEPROM_BLK_U32_LEN: u16 = 16; // Number of the words in a block
const EEPROM_PRETRY: u32 = 0x00000004; // Programming Must Be Retried
const EEPROM_ERETRY: u32 = 0x00000008; // Erase Must Be Retried
pub const BLK_COUNT: u16 = 96; // Number of blocks
pub const BLK_U32_LEN: usize = 16; // Number of words in a block
const PRETRY: u32 = 0x00000004; // Programming Must Be Retried
const ERETRY: u32 = 0x00000008; // Erase Must Be Retried
fn wait_done() {
unsafe {
let eeprom = tm4c129x::EEPROM.get();
// Make sure the EEPROM is idle
while (*eeprom).eedone.read().working().bit() {};
}
while cortex_m::interrupt::free(|cs| {
let eeprom = tm4c129x::EEPROM.borrow(cs);
eeprom.eedone.read().working().bit()
}) {};
}
pub fn init() -> u32 {
let status: u32 = 0;
pub fn init() {
cortex_m::interrupt::free(|cs| {
let sysctl = tm4c129x::SYSCTL.borrow(cs);
let eeprom = tm4c129x::EEPROM.borrow(cs);
sysctl.rcgceeprom.modify(|_, w| w.r0().bit(true)); // Bring up EEPROM
delay(16);
let eesupp1 = eeprom.eesupp.read().bits();
if 0 != eesupp1 & (EEPROM_PRETRY | EEPROM_ERETRY) {
println!("eesupp1:{}", eesupp1)
}
board::delay(16);
sysctl.sreeprom.modify(|_, w| w.r0().bit(true)); // Activate EEPROM reset
delay(16);
board::delay(16);
sysctl.sreeprom.modify(|_, w| w.r0().bit(false)); // Dectivate EEPROM reset
delay(16);
board::delay(16);
while !sysctl.preeprom.read().r0().bit() {} // Wait for the EEPROM to come out of reset
delay(16);
wait_done();
let eesupp2 = eeprom.eesupp.read().bits();
if 0 != eesupp2 & (EEPROM_PRETRY | EEPROM_ERETRY) {
println!("eesupp2:{}", eesupp2)
}
let eesize_blkcnt = eeprom.eesize.read().blkcnt().bits();
println!("EESIZE_BLK:{}", eesize_blkcnt)
board::delay(16);
});
status
wait_done();
}
pub fn mass_erase() {
pub fn mass_erase() -> bool {
wait_done();
cortex_m::interrupt::free(|cs| {
let eeprom = tm4c129x::EEPROM.borrow(cs);
@ -58,66 +40,49 @@ pub fn mass_erase() {
wait_done();
cortex_m::interrupt::free(|cs| {
let sysctl = tm4c129x::SYSCTL.borrow(cs);
let eeprom = tm4c129x::EEPROM.borrow(cs);
sysctl.sreeprom.modify(|_, w| w.r0().bit(true)); // Activate EEPROM reset
delay(16);
board::delay(16);
sysctl.sreeprom.modify(|_, w| w.r0().bit(false)); // Dectivate EEPROM reset
delay(16);
board::delay(16);
while !sysctl.preeprom.read().r0().bit() {} // Wait for the EEPROM to come out of reset
delay(16);
board::delay(16);
});
wait_done();
cortex_m::interrupt::free(|cs| {
let sysctl = tm4c129x::SYSCTL.borrow(cs);
let eeprom = tm4c129x::EEPROM.borrow(cs);
let eesupp2 = eeprom.eesupp.read().bits();
if 0 != eesupp2 & (EEPROM_PRETRY | EEPROM_ERETRY) {
println!("eesupp2:{}", eesupp2)
} else {
println!("erase_ok");
}
});
eesupp2 & (PRETRY | ERETRY) == 0
})
}
pub fn read_blk(buf: &mut [u32; 16], blk: u16, verify: bool) -> u8 {
let mut result : u8 = 0;
assert!(blk < EEPROM_BLK_COUNT);
wait_done();
pub fn read_blk(buf: &mut [u32; BLK_U32_LEN], blk: u16) {
assert!(blk < BLK_COUNT);
cortex_m::interrupt::free(|cs| {
let eeprom = tm4c129x::EEPROM.borrow(cs);
eeprom.eeblock.write(|w| unsafe { w.block().bits(blk) });
eeprom.eeoffset.write(|w| unsafe { w.offset().bits(0) });
});
for i in 0..EEPROM_BLK_U32_LEN {
for i in 0..BLK_U32_LEN {
cortex_m::interrupt::free(|cs| {
let eeprom = tm4c129x::EEPROM.borrow(cs);
if verify {
if buf[i as usize] != eeprom.eerdwrinc.read().bits() {
result += 1;
}
} else {
buf[i as usize] = eeprom.eerdwrinc.read().bits();
}
buf[i] = eeprom.eerdwrinc.read().bits();
});
}
result
}
pub fn write_blk(buf: &[u32; 16], blk: u16) -> u8 {
assert!(blk < EEPROM_BLK_COUNT);
wait_done();
pub fn write_blk(buf: &[u32; BLK_U32_LEN], blk: u16) {
assert!(blk < BLK_COUNT);
cortex_m::interrupt::free(|cs| {
let eeprom = tm4c129x::EEPROM.borrow(cs);
eeprom.eeblock.write(|w| unsafe { w.block().bits(blk) });
eeprom.eeoffset.write(|w| unsafe { w.offset().bits(0) });
});
for i in 0..EEPROM_BLK_U32_LEN {
for i in 0..BLK_U32_LEN {
cortex_m::interrupt::free(|cs| {
let eeprom = tm4c129x::EEPROM.borrow(cs);
eeprom.eerdwrinc.write(|w| unsafe { w.bits(buf[i as usize]) });
eeprom.eerdwrinc.write(|w| unsafe { w.bits(buf[i]) });
});
delay(16);
board::delay(16);
wait_done();
}
0
}
}

23
firmware/src/ethmac.rs
View File

@ -1,11 +1,12 @@
use core::slice;
use cortex_m;
use tm4c129x;
use core::slice;
use smoltcp::Error;
use smoltcp::wire::EthernetAddress;
use smoltcp::phy::{DeviceLimits, Device};
use board;
const EPHY_BMCR: u8 = 0x00; // Ethernet PHY Basic Mode Control
#[allow(dead_code)]
const EPHY_BMSR: u8 = 0x01; // Ethernet PHY Basic Mode Status
@ -39,16 +40,6 @@ const ETH_TX_BUFFER_SIZE: usize = 1536;
const ETH_RX_BUFFER_COUNT: usize = 3;
const ETH_RX_BUFFER_SIZE: usize = 1536;
fn delay(d: u32) {
for _ in 0..d {
unsafe {
asm!("
NOP
");
}
}
}
fn phy_read(reg_addr: u8) -> u16 {
cortex_m::interrupt::free(|cs| {
let emac0 = tm4c129x::EMAC0.borrow(cs);
@ -189,21 +180,21 @@ impl EthernetDevice {
sysctl.rcgcemac.modify(|_, w| w.r0().bit(true)); // Bring up MAC
sysctl.sremac.modify(|_, w| w.r0().bit(true)); // Activate MAC reset
delay(16);
board::delay(16);
sysctl.sremac.modify(|_, w| w.r0().bit(false)); // Dectivate MAC reset
sysctl.rcgcephy.modify(|_, w| w.r0().bit(true)); // Bring up PHY
sysctl.srephy.modify(|_, w| w.r0().bit(true)); // Activate PHY reset
delay(16);
board::delay(16);
sysctl.srephy.modify(|_, w| w.r0().bit(false)); // Dectivate PHY reset
while !sysctl.premac.read().r0().bit() {} // Wait for the MAC to come out of reset
while !sysctl.prephy.read().r0().bit() {} // Wait for the PHY to come out of reset
delay(10000);
board::delay(10000);
emac0.dmabusmod.modify(|_, w| w.swr().bit(true)); // Reset MAC DMA
while emac0.dmabusmod.read().swr().bit() {} // Wait for the MAC DMA to come out of reset
delay(1000);
board::delay(1000);
emac0.miiaddr.write(|w| w.cr()._100_150()); // Set the MII CSR clock speed.

1
firmware/src/main.rs
View File

@ -39,6 +39,7 @@ pub fn panic_fmt(args: core::fmt::Arguments, file: &'static str, line: u32) -> !
#[macro_use]
mod board;
mod eeprom;
mod ethmac;
mod pid;
mod loop_anode;