Rewrite ethmac to split ownership into RX/TX halves.
whitequark
parent
5a5596f7a2
commit
308ad97586
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@ -100,82 +100,176 @@ fn phy_write_ext(reg_addr: u8, reg_data: u16) {
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phy_write(EPHY_ADDAR, reg_data);
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}
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struct DeviceInner {
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tx_desc_buf: [u32; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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rx_desc_buf: [u32; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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tx_cur_desc: usize,
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rx_cur_desc: usize,
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tx_counter: u32,
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rx_counter: u32,
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tx_pkt_buf: [u8; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
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rx_pkt_buf: [u8; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
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struct RxRing {
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desc_buf: [u32; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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cur_desc: usize,
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counter: u32,
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pkt_buf: [u8; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
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}
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impl DeviceInner {
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fn new() -> DeviceInner {
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DeviceInner {
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tx_desc_buf: [0; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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rx_desc_buf: [0; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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tx_cur_desc: 0,
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rx_cur_desc: 0,
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tx_counter: 0,
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rx_counter: 0,
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tx_pkt_buf: [0; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
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rx_pkt_buf: [0; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
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impl RxRing {
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fn new() -> RxRing {
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RxRing {
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desc_buf: [0; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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cur_desc: 0,
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counter: 0,
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pkt_buf: [0; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
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}
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}
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fn init(&mut self, mac_addr: EthernetAddress) {
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// Initialize TX DMA descriptors
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for x in 0..ETH_TX_BUFFER_COUNT {
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let p = x * ETH_DESC_U32_SIZE;
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let r = x * ETH_TX_BUFFER_SIZE;
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// Initialize transmit flags
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self.tx_desc_buf[p + 0] = 0;
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// Initialize transmit buffer size
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self.tx_desc_buf[p + 1] = 0;
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// Transmit buffer address
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self.tx_desc_buf[p + 2] = (&self.tx_pkt_buf[r] as *const u8) as u32;
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// Next descriptor address
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if x != ETH_TX_BUFFER_COUNT - 1 {
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self.tx_desc_buf[p + 3] = (&self.tx_desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
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} else {
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self.tx_desc_buf[p + 3] = (&self.tx_desc_buf[0] as *const u32) as u32;
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}
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// Reserved fields
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self.tx_desc_buf[p + 4] = 0;
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self.tx_desc_buf[p + 5] = 0;
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// Transmit frame time stamp
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self.tx_desc_buf[p + 6] = 0;
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self.tx_desc_buf[p + 7] = 0;
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}
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fn init(&mut self) {
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// Initialize RX DMA descriptors
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for x in 0..ETH_RX_BUFFER_COUNT {
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let p = x * ETH_DESC_U32_SIZE;
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let r = x * ETH_RX_BUFFER_SIZE;
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// The descriptor is initially owned by the DMA
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self.rx_desc_buf[p + 0] = EMAC_RDES0_OWN;
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self.desc_buf[p + 0] = EMAC_RDES0_OWN;
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// Use chain structure rather than ring structure
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self.rx_desc_buf[p + 1] = EMAC_RDES1_RCH | ((ETH_RX_BUFFER_SIZE as u32) & EMAC_RDES1_RBS1);
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self.desc_buf[p + 1] =
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EMAC_RDES1_RCH | ((ETH_RX_BUFFER_SIZE as u32) & EMAC_RDES1_RBS1);
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// Receive buffer address
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self.rx_desc_buf[p + 2] = (&self.rx_pkt_buf[r] as *const u8) as u32;
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self.desc_buf[p + 2] = (&self.pkt_buf[r] as *const u8) as u32;
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// Next descriptor address
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if x != ETH_RX_BUFFER_COUNT - 1 {
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self.rx_desc_buf[p + 3] = (&self.rx_desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
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self.desc_buf[p + 3] =
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(&self.desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
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} else {
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self.rx_desc_buf[p + 3] = (&self.rx_desc_buf[0] as *const u32) as u32;
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self.desc_buf[p + 3] =
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(&self.desc_buf[0] as *const u32) as u32;
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}
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// Extended status
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self.rx_desc_buf[p + 4] = 0;
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self.desc_buf[p + 4] = 0;
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// Reserved field
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self.rx_desc_buf[p + 5] = 0;
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self.desc_buf[p + 5] = 0;
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// Transmit frame time stamp
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self.rx_desc_buf[p + 6] = 0;
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self.rx_desc_buf[p + 7] = 0;
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self.desc_buf[p + 6] = 0;
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self.desc_buf[p + 7] = 0;
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}
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}
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fn buf_owned(&self) -> bool {
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self.desc_buf[self.cur_desc + 0] & EMAC_RDES0_OWN == 0
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}
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fn buf_valid(&self) -> bool {
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self.desc_buf[self.cur_desc + 0] &
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(EMAC_RDES0_FS | EMAC_RDES0_LS | EMAC_RDES0_ES) ==
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(EMAC_RDES0_FS | EMAC_RDES0_LS)
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}
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unsafe fn buf_as_slice<'a>(&self) -> &'a [u8] {
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let len = (self.desc_buf[self.cur_desc + 0] & EMAC_RDES0_FL) >> 16;
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let len = cmp::min(len as usize, ETH_RX_BUFFER_SIZE);
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let addr = self.desc_buf[self.cur_desc + 2] as *const u8;
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slice::from_raw_parts(addr, len)
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}
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fn buf_release(&mut self) {
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self.desc_buf[self.cur_desc + 0] = EMAC_RDES0_OWN;
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self.cur_desc += ETH_DESC_U32_SIZE;
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if self.cur_desc == self.desc_buf.len() {
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self.cur_desc = 0;
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}
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self.counter += 1;
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}
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}
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struct TxRing {
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desc_buf: [u32; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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cur_desc: usize,
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counter: u32,
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pkt_buf: [u8; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
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}
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impl TxRing {
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fn new() -> TxRing {
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TxRing {
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desc_buf: [0; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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cur_desc: 0,
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counter: 0,
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pkt_buf: [0; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
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}
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}
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fn init(&mut self) {
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// Initialize TX DMA descriptors
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for x in 0..ETH_TX_BUFFER_COUNT {
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let p = x * ETH_DESC_U32_SIZE;
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let r = x * ETH_TX_BUFFER_SIZE;
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// Initialize transmit flags
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self.desc_buf[p + 0] = 0;
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// Initialize transmit buffer size
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self.desc_buf[p + 1] = 0;
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// Transmit buffer address
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self.desc_buf[p + 2] = (&self.pkt_buf[r] as *const u8) as u32;
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// Next descriptor address
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if x != ETH_TX_BUFFER_COUNT - 1 {
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self.desc_buf[p + 3] =
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(&self.desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
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} else {
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self.desc_buf[p + 3] =
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(&self.desc_buf[0] as *const u32) as u32;
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}
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// Reserved fields
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self.desc_buf[p + 4] = 0;
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self.desc_buf[p + 5] = 0;
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// Transmit frame time stamp
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self.desc_buf[p + 6] = 0;
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self.desc_buf[p + 7] = 0;
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}
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}
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fn buf_owned(&self) -> bool {
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self.desc_buf[self.cur_desc + 0] & EMAC_TDES0_OWN == 0
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}
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unsafe fn buf_as_slice<'a>(&mut self, len: usize) -> &'a mut [u8] {
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let len = cmp::min(len, ETH_TX_BUFFER_SIZE);
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self.desc_buf[self.cur_desc + 1] = len as u32;
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let addr = self.desc_buf[self.cur_desc + 2] as *mut u8;
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slice::from_raw_parts_mut(addr, len)
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}
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fn buf_release(&mut self) {
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self.desc_buf[self.cur_desc + 0] =
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EMAC_TDES0_OWN | EMAC_TDES0_LS | EMAC_TDES0_FS | EMAC_TDES0_TCH;
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cortex_m::interrupt::free(|cs| {
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let emac0 = tm4c129x::EMAC0.borrow(cs);
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// Clear TU flag to resume processing
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emac0.dmaris.write(|w| w.tu().bit(true));
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// Instruct the DMA to poll the transmit descriptor list
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unsafe { emac0.txpolld.write(|w| w.tpd().bits(0)); }
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});
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self.cur_desc += ETH_DESC_U32_SIZE;
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if self.cur_desc == self.desc_buf.len() {
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self.cur_desc = 0;
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}
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self.counter += 1;
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}
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}
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pub struct Device {
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rx: RxRing,
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tx: TxRing,
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}
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impl Device {
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pub fn new() -> Device {
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Device {
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rx: RxRing::new(),
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tx: TxRing::new(),
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}
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}
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// After `init` is called, `Device` shall not be moved.
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pub unsafe fn init(&mut self, mac: EthernetAddress) {
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self.rx.init();
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self.tx.init();
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cortex_m::interrupt::free(|cs| {
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let sysctl = tm4c129x::SYSCTL.borrow(cs);
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@ -254,17 +348,22 @@ impl DeviceInner {
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});
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// Set the MAC address
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let mac_addr = mac_addr.0;
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emac0.addr0h.write(|w| unsafe { w.addrhi().bits(mac_addr[4] as u16 | ((mac_addr[5] as u16) << 8)) });
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emac0.addr0l.write(|w| unsafe {
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w.addrlo().bits(mac_addr[0] as u32 | ((mac_addr[1] as u32) << 8) | ((mac_addr[2] as u32) << 16) | ((mac_addr[3] as u32) << 24))
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w.addrlo().bits( mac.0[0] as u32 |
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((mac.0[1] as u32) << 8) |
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((mac.0[2] as u32) << 16) |
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((mac.0[3] as u32) << 24))
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});
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emac0.addr0h.write(|w| unsafe {
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w.addrhi().bits( mac.0[4] as u16 |
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((mac.0[5] as u16) << 8))
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});
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// Set MAC filtering options (?)
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emac0.framefltr.write(|w|
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w.hpf().bit(true) // Hash or Perfect Filter
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//.hmc().bit(true) // Hash Multicast ???
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.pm().bit(true) // Pass All Multicast
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.pm().bit(true) // Pass All Multicast
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);
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// Initialize hash table
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@ -273,96 +372,26 @@ impl DeviceInner {
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emac0.flowctl.write(|w| unsafe { w.bits(0)}); // Disable flow control ???
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emac0.txdladdr.write(|w| unsafe { w.bits((&self.tx_desc_buf[0] as *const u32) as u32)});
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emac0.rxdladdr.write(|w| unsafe { w.bits((&self.rx_desc_buf[0] as *const u32) as u32)});
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emac0.txdladdr.write(|w| unsafe {
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w.bits((&mut self.tx.desc_buf[0] as *mut u32) as u32)
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});
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emac0.rxdladdr.write(|w| unsafe {
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w.bits((&mut self.rx.desc_buf[0] as *mut u32) as u32)
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});
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// Manage MAC transmission and reception
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emac0.cfg.modify(|_, w|
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w.re().bit(true) // Receiver Enable
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.te().bit(true) // Transmiter Enable
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.te().bit(true) // Transmiter Enable
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);
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// Manage DMA transmission and reception
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emac0.dmaopmode.modify(|_, w|
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w.sr().bit(true) // Start Receive
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.st().bit(true) // Start Transmit
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.st().bit(true) // Start Transmit
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);
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});
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}
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// RX buffer functions
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fn rx_buf_owned(&self) -> bool {
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self.rx_desc_buf[self.rx_cur_desc + 0] & EMAC_RDES0_OWN == 0
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}
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fn rx_buf_valid(&self) -> bool {
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self.rx_desc_buf[self.rx_cur_desc + 0] &
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(EMAC_RDES0_FS | EMAC_RDES0_LS | EMAC_RDES0_ES) ==
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(EMAC_RDES0_FS | EMAC_RDES0_LS)
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}
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unsafe fn rx_buf_as_slice<'a>(&self) -> &'a [u8] {
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let len = (self.rx_desc_buf[self.rx_cur_desc + 0] & EMAC_RDES0_FL) >> 16;
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let len = cmp::min(len as usize, ETH_RX_BUFFER_SIZE);
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let addr = self.rx_desc_buf[self.rx_cur_desc + 2] as *const u8;
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slice::from_raw_parts(addr, len)
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}
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fn rx_buf_release(&mut self) {
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self.rx_desc_buf[self.rx_cur_desc + 0] = EMAC_RDES0_OWN;
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self.rx_cur_desc += ETH_DESC_U32_SIZE;
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if self.rx_cur_desc == self.rx_desc_buf.len() {
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self.rx_cur_desc = 0;
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}
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self.rx_counter += 1;
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}
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// TX buffer functions
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fn tx_buf_owned(&self) -> bool {
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self.tx_desc_buf[self.tx_cur_desc + 0] & EMAC_TDES0_OWN == 0
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}
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unsafe fn tx_buf_as_slice<'a>(&mut self, len: usize) -> &'a mut [u8] {
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let len = cmp::min(len, ETH_TX_BUFFER_SIZE);
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self.tx_desc_buf[self.tx_cur_desc + 1] = len as u32;
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let addr = self.tx_desc_buf[self.tx_cur_desc + 2] as *mut u8;
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slice::from_raw_parts_mut(addr, len)
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}
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fn tx_buf_release(&mut self) {
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self.tx_desc_buf[self.tx_cur_desc + 0] =
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EMAC_TDES0_OWN | EMAC_TDES0_LS | EMAC_TDES0_FS | EMAC_TDES0_TCH;
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cortex_m::interrupt::free(|cs| {
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let emac0 = tm4c129x::EMAC0.borrow(cs);
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// Clear TU flag to resume processing
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emac0.dmaris.write(|w| w.tu().bit(true));
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// Instruct the DMA to poll the transmit descriptor list
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unsafe { emac0.txpolld.write(|w| w.tpd().bits(0)); }
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});
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self.tx_cur_desc += ETH_DESC_U32_SIZE;
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if self.tx_cur_desc == self.tx_desc_buf.len() {
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self.tx_cur_desc = 0;
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}
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self.tx_counter += 1;
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}
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}
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pub struct Device(RefCell<DeviceInner>);
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impl Device {
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pub fn new() -> Device {
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Device(RefCell::new(DeviceInner::new()))
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}
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// After `init` is called, `Device` shall not be moved.
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pub unsafe fn init(&mut self, mac: EthernetAddress) {
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self.0.borrow_mut().init(mac);
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}
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}
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impl<'a, 'b> phy::Device<'a> for &'b mut Device {
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@ -377,55 +406,45 @@ impl<'a, 'b> phy::Device<'a> for &'b mut Device {
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}
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fn receive(&mut self) -> Option<(RxToken, TxToken)> {
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{
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let mut device = self.0.borrow_mut();
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// Skip all queued packets with errors.
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while device.rx_buf_owned() && !device.rx_buf_valid() {
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device.rx_buf_release()
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}
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if !(device.rx_buf_owned() && device.tx_buf_owned()) {
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return None
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}
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// Skip all queued packets with errors.
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while self.rx.buf_owned() && !self.rx.buf_valid() {
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self.rx.buf_release()
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}
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Some((RxToken(&self.0), TxToken(&self.0)))
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if !(self.rx.buf_owned() && self.tx.buf_owned()) {
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return None
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}
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Some((RxToken(&mut self.rx), TxToken(&mut self.tx)))
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}
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fn transmit(&mut self) -> Option<TxToken> {
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{
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let device = self.0.borrow_mut();
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if !device.tx_buf_owned() {
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return None
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}
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if !self.tx.buf_owned() {
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return None
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}
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Some(TxToken(&self.0))
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Some(TxToken(&mut self.tx))
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}
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}
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pub struct RxToken<'a>(&'a RefCell<DeviceInner>);
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pub struct RxToken<'a>(&'a mut RxRing);
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impl<'a> phy::RxToken for RxToken<'a> {
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fn consume<R, F>(self, _timestamp: Instant, f: F) -> Result<R>
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where F: FnOnce(&[u8]) -> Result<R> {
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let mut device = self.0.borrow_mut();
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let result = f(unsafe { device.rx_buf_as_slice() });
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device.rx_buf_release();
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let result = f(unsafe { self.0.buf_as_slice() });
|
||||
self.0.buf_release();
|
||||
result
|
||||
}
|
||||
}
|
||||
|
||||
pub struct TxToken<'a>(&'a RefCell<DeviceInner>);
|
||||
pub struct TxToken<'a>(&'a mut TxRing);
|
||||
|
||||
impl<'a> phy::TxToken for TxToken<'a> {
|
||||
fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> Result<R>
|
||||
where F: FnOnce(&mut [u8]) -> Result<R> {
|
||||
let mut device = self.0.borrow_mut();
|
||||
let result = f(unsafe { device.tx_buf_as_slice(len) });
|
||||
device.tx_buf_release();
|
||||
let result = f(unsafe { self.0.buf_as_slice(len) });
|
||||
self.0.buf_release();
|
||||
result
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue