147 lines
4.9 KiB
Rust
147 lines
4.9 KiB
Rust
use cortex_m;
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use tm4c129x;
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pub mod gpio;
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pub mod softspi;
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pub mod systick;
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pub mod pwm;
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const UART_DIV: u32 = (((/*sysclk*/120_000_000 * 8) / /*baud*/115200) + 1) / 2;
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pub fn init() {
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cortex_m::interrupt::free(|cs| {
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let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
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// Set up main oscillator
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sysctl.moscctl.write(|w| w.noxtal().bit(false));
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sysctl.moscctl.modify(|_, w| w.pwrdn().bit(false).oscrng().bit(true));
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// Prepare flash for the high-freq clk
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sysctl.memtim0.write(|w| unsafe { w.bits(0x01950195u32) });
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sysctl.rsclkcfg.write(|w| unsafe { w.bits(0x80000000u32) });
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// Set up PLL with fVCO=480 MHz
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sysctl.pllfreq1.write(|w| w.q().bits(0).n().bits(4));
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sysctl.pllfreq0.write(|w| w.mint().bits(96).pllpwr().bit(true));
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sysctl.rsclkcfg.modify(|_, w| w.pllsrc().mosc().newfreq().bit(true));
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while !sysctl.pllstat.read().lock().bit() {}
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// Switch to PLL (sysclk=120MHz)
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sysctl.rsclkcfg.write(|w| unsafe { w.bits(0b1_0_0_1_0011_0000_0000000000_0000000011) });
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// Bring up GPIO ports A, B, D, E, F, G, K, L, M, P, Q
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sysctl.rcgcgpio.modify(|_, w| {
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w.r0().bit(true)
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.r1().bit(true)
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.r3().bit(true)
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.r4().bit(true)
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.r5().bit(true)
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.r6().bit(true)
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.r9().bit(true)
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.r10().bit(true)
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.r11().bit(true)
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.r13().bit(true)
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.r14().bit(true)
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});
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while !sysctl.prgpio.read().r0().bit() {}
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while !sysctl.prgpio.read().r1().bit() {}
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while !sysctl.prgpio.read().r3().bit() {}
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while !sysctl.prgpio.read().r4().bit() {}
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while !sysctl.prgpio.read().r5().bit() {}
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while !sysctl.prgpio.read().r6().bit() {}
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while !sysctl.prgpio.read().r9().bit() {}
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while !sysctl.prgpio.read().r10().bit() {}
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while !sysctl.prgpio.read().r11().bit() {}
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while !sysctl.prgpio.read().r13().bit() {}
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while !sysctl.prgpio.read().r14().bit() {}
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// Set up UART0
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let gpio_a = unsafe { &*tm4c129x::GPIO_PORTA_AHB::ptr() };
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gpio_a.dir.write(|w| w.dir().bits(0b11));
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gpio_a.den.write(|w| w.den().bits(0b11));
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gpio_a.afsel.write(|w| w.afsel().bits(0b11));
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gpio_a.pctl.write(|w| unsafe { w.pmc0().bits(1).pmc1().bits(1) });
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sysctl.rcgcuart.modify(|_, w| w.r0().bit(true));
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while !sysctl.pruart.read().r0().bit() {}
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let uart_0 = unsafe { &*tm4c129x::UART0::ptr() };
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uart_0.cc.write(|w| w.cs().sysclk());
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uart_0.ibrd.write(|w| w.divint().bits((UART_DIV / 64) as u16));
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uart_0.fbrd.write(|w| w.divfrac().bits((UART_DIV % 64) as u8));
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uart_0.lcrh.write(|w| w.wlen()._8().fen().bit(true));
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uart_0.ctl.write(|w| w.rxe().bit(true).txe().bit(true).uarten().bit(true));
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// Set up PWMs
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let gpio_m = unsafe { &*tm4c129x::GPIO_PORTM::ptr() };
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// Output
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gpio_m.dir.write(|w| w.dir().bits(0xff));
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// Enable
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gpio_m.den.write(|w| w.den().bits(0xff));
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// Alternate function
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gpio_m.afsel.write(|w| w.afsel().bits(0xff));
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// Function: Timer PWM
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gpio_m.pctl.write(|w| unsafe {
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w
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// t2ccp0
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.pmc0().bits(3)
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// t2ccp1
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.pmc1().bits(3)
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// t3ccp0
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.pmc2().bits(3)
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// t3ccp1
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.pmc3().bits(3)
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// t4ccp0
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.pmc4().bits(3)
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// t4ccp1
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.pmc5().bits(3)
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// t5ccp0
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.pmc6().bits(3)
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// t5ccp1
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.pmc7().bits(3)
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});
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// Enable timers
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sysctl.rcgctimer.write(|w| w
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.r2().set_bit()
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.r3().set_bit()
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.r4().set_bit()
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.r5().set_bit()
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);
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// Reset timers
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sysctl.srtimer.write(|w| w
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.r2().set_bit()
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.r3().set_bit()
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.r4().set_bit()
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.r5().set_bit()
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);
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sysctl.srtimer.write(|w| w
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.r2().clear_bit()
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.r3().clear_bit()
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.r4().clear_bit()
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.r5().clear_bit()
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);
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fn timers_ready(sysctl: &tm4c129x::sysctl::RegisterBlock) -> bool {
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let prtimer = sysctl.prtimer.read();
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prtimer.r2().bit() &&
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prtimer.r3().bit() &&
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prtimer.r4().bit() &&
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prtimer.r5().bit()
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}
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while !timers_ready(sysctl) {}
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systick::init(cs);
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});
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}
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pub fn get_mac_address() -> [u8; 6] {
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let (userreg0, userreg1) = cortex_m::interrupt::free(|_cs| {
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let flashctl = unsafe { &*tm4c129x::FLASH_CTRL::ptr() };
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(flashctl.userreg0.read().bits(),
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flashctl.userreg1.read().bits())
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});
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[userreg0 as u8, (userreg0 >> 8) as u8, (userreg0 >> 16) as u8,
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userreg1 as u8, (userreg1 >> 8) as u8, (userreg1 >> 16) as u8]
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}
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