ad7172: break out mods adc, checksum, regs
This commit is contained in:
parent
98a5788770
commit
8b2cc15d7d
@ -1,367 +0,0 @@
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::spi::Transfer;
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use byteorder::{BigEndian, ByteOrder};
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use bit_field::BitField;
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trait Register {
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type Data: RegisterData;
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fn address(&self) -> u8;
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}
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trait RegisterData {
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fn empty() -> Self;
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fn as_mut(&mut self) -> &mut [u8];
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}
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macro_rules! def_reg {
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($Reg: ident, $reg: ident, $addr: expr, $size: expr) => {
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struct $Reg;
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impl Register for $Reg {
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type Data = $reg::Data;
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fn address(&self) -> u8 {
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$addr
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}
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}
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mod $reg {
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pub struct Data(pub [u8; $size]);
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impl super::RegisterData for Data {
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fn empty() -> Self {
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Data([0; $size])
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}
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fn as_mut(&mut self) -> &mut [u8] {
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&mut self.0
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}
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}
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}
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};
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($Reg: ident, $index: ty, $reg: ident, $addr: expr, $size: expr) => {
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struct $Reg { pub index: $index, }
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impl Register for $Reg {
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type Data = $reg::Data;
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fn address(&self) -> u8 {
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$addr + (self.index as u8)
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}
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}
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mod $reg {
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pub struct Data(pub [u8; $size]);
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impl super::RegisterData for Data {
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fn empty() -> Self {
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Data([0; $size])
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}
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fn as_mut(&mut self) -> &mut [u8] {
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&mut self.0
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}
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}
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}
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}
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}
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def_reg!(Status, status, 0x00, 1);
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impl status::Data {
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/// Is there new data to read?
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fn ready(&self) -> bool {
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! self.0[0].get_bit(7)
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}
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/// Channel for which data is ready
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fn channel(&self) -> u8 {
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self.0[0].get_bits(0..=1)
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}
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fn adc_error(&self) -> bool {
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self.0[0].get_bit(6)
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}
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fn crc_error(&self) -> bool {
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self.0[0].get_bit(5)
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}
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fn reg_error(&self) -> bool {
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self.0[0].get_bit(4)
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}
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}
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def_reg!(IfMode, if_mode, 0x02, 2);
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impl if_mode::Data {
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fn set_crc(&mut self, mode: ChecksumMode) {
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self.0[1].set_bits(2..=3, mode as u8);
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}
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}
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def_reg!(Data, data, 0x04, 3);
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impl data::Data {
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fn data(&self) -> u32 {
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(u32::from(self.0[0]) << 16) |
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(u32::from(self.0[1]) << 8) |
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u32::from(self.0[2])
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}
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}
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def_reg!(Id, id, 0x07, 2);
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impl id::Data {
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fn id(&self) -> u16 {
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BigEndian::read_u16(&self.0)
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}
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}
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def_reg!(Channel, u8, channel, 0x10, 2);
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impl channel::Data {
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fn enabled(&self) -> bool {
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self.0[0].get_bit(7)
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}
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fn set_enabled(&mut self, value: bool) {
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self.0[0].set_bit(7, value);
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}
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}
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def_reg!(SetupCon, u8, setup_con, 0x20, 2);
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def_reg!(FiltCon, u8, filt_con, 0x80, 2);
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// #[allow(unused)]
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// #[derive(Clone, Copy)]
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// #[repr(u8)]
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// pub enum Register {
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// Status = 0x00,
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// AdcMode = 0x01,
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// IfMode = 0x02,
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// RegCheck = 0x03,
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// Data = 0x04,
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// GpioCon = 0x06,
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// Id = 0x07,
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// Ch0 = 0x10,
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// Ch1 = 0x11,
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// Ch2 = 0x12,
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// Ch3 = 0x13,
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// SetupCon0 = 0x20,
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// SetupCon1 = 0x21,
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// SetupCon2 = 0x22,
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// SetupCon3 = 0x23,
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// FiltCon0 = 0x28,
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// FiltCon1 = 0x29,
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// FiltCon2 = 0x2A,
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// FiltCon3 = 0x2B,
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// Offset0 = 0x30,
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// Offset1 = 0x31,
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// Offset2 = 0x32,
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// Offset3 = 0x33,
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// Gain0 = 0x38,
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// Gain1 = 0x39,
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// Gain2 = 0x3A,
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// Gain3 = 0x3B,
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// }
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#[repr(u8)]
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pub enum Input {
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Ain0 = 0,
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Ain1 = 1,
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Ain2 = 2,
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Ain3 = 3,
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Ain4 = 4,
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TemperaturePos = 17,
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TemperatureNeg = 18,
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AnalogSupplyPos = 19,
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AnalogSupplyNeg = 20,
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RefPos = 21,
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RefNeg = 22,
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}
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#[derive(Clone, Debug, PartialEq)]
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pub enum AdcError<SPI> {
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SPI(SPI),
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ChecksumMismatch(Option<u8>, Option<u8>),
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}
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impl<SPI> From<SPI> for AdcError<SPI> {
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fn from(e: SPI) -> Self {
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AdcError::SPI(e)
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}
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}
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#[derive(Clone, Copy, PartialEq)]
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#[repr(u8)]
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pub enum ChecksumMode {
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Off = 0b00,
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/// Seems much less reliable than `Crc`
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Xor = 0b01,
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Crc = 0b10,
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}
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struct Checksum {
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mode: ChecksumMode,
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state: u8,
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}
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impl Checksum {
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pub fn new(mode: ChecksumMode) -> Self {
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Checksum { mode, state: 0 }
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}
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pub fn feed(&mut self, input: u8) {
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match self.mode {
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ChecksumMode::Off => {},
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ChecksumMode::Xor => self.state ^= input,
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ChecksumMode::Crc => {
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for i in 0..8 {
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let input_mask = 0x80 >> i;
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self.state = (self.state << 1) ^
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if ((self.state & 0x80) != 0) != ((input & input_mask) != 0) {
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0x07 /* x8 + x2 + x + 1 */
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} else {
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0
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};
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}
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}
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}
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}
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pub fn result(&self) -> Option<u8> {
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match self.mode {
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ChecksumMode::Off => None,
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_ => Some(self.state)
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}
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}
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}
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/// AD7172-2 implementation
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///
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/// [Manual](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf)
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pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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checksum_mode: ChecksumMode,
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}
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impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
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let _ = nss.set_high();
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let mut adc = Adc {
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spi, nss,
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checksum_mode: ChecksumMode::Off,
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};
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adc.reset()?;
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Ok(adc)
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}
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/// `0x00DX` for AD7271-2
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pub fn identify(&mut self) -> Result<u16, AdcError<SPI::Error>> {
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self.read_reg(&Id)
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.map(|id| id.id())
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}
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), AdcError<SPI::Error>> {
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let mut ifmode = self.read_reg(&IfMode)?;
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ifmode.set_crc(mode);
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self.checksum_mode = mode;
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self.write_reg(&IfMode, &mut ifmode)?;
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Ok(())
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}
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// pub fn setup(&mut self) -> Result<(), SPI::Error> {
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// let mut buf = [0, 0, 0];
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// adc.write_reg(Register::AdcMode, &mut buf)?;
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// let mut buf = [0, 1, 0];
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// adc.write_reg(Register::IfMode, &mut buf)?;
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// let mut buf = [0, 0, 0];
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// adc.write_reg(Register::GpioCon, &mut buf)?;
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// Ok(())
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// }
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/// Returns the channel the data is from
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pub fn data_ready(&mut self) -> Result<Option<u8>, AdcError<SPI::Error>> {
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self.read_reg(&Status)
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.map(|status| {
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if status.ready() {
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Some(status.channel())
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} else {
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None
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}
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})
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}
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/// Get data
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pub fn read_data(&mut self) -> Result<u32, AdcError<SPI::Error>> {
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self.read_reg(&Data)
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.map(|data| data.data())
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}
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fn read_reg<R: Register>(&mut self, reg: &R) -> Result<R::Data, AdcError<SPI::Error>> {
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let mut reg_data = R::Data::empty();
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let address = 0x40 | reg.address();
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let mut checksum = Checksum::new(self.checksum_mode);
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checksum.feed(address);
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let checksum_out = checksum.result();
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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for &mut b in reg_data.as_mut() {
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checksum.feed(b);
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}
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let checksum_expected = checksum.result();
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if checksum_expected != checksum_in {
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return Err(AdcError::ChecksumMismatch(checksum_expected, checksum_in));
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}
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Ok(reg_data)
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}
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fn write_reg<R: Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), AdcError<SPI::Error>> {
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let address = reg.address();
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let mut checksum = Checksum::new(match self.checksum_mode {
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ChecksumMode::Off => ChecksumMode::Off,
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// write checksums are always crc
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ChecksumMode::Xor => ChecksumMode::Crc,
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ChecksumMode::Crc => ChecksumMode::Crc,
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});
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checksum.feed(address);
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for &mut b in reg_data.as_mut() {
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checksum.feed(b);
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}
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let checksum_out = checksum.result();
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self.transfer(address, reg_data.as_mut(), checksum_out)?;
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Ok(())
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}
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, AdcError<SPI::Error>>
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where
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R: Register,
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F: FnOnce(&mut R::Data) -> A,
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{
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let mut reg_data = self.read_reg(reg)?;
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let result = f(&mut reg_data);
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self.write_reg(reg, &mut reg_data)?;
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Ok(result)
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}
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pub fn reset(&mut self) -> Result<(), SPI::Error> {
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let mut buf = [0xFFu8; 8];
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let _ = self.nss.set_low();
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let result = self.spi.transfer(&mut buf);
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let _ = self.nss.set_high();
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result?;
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Ok(())
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}
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fn transfer<'w>(&mut self, addr: u8, reg_data: &'w mut [u8], checksum: Option<u8>) -> Result<Option<u8>, SPI::Error> {
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let mut addr_buf = [addr];
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let _ = self.nss.set_low();
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let result = match self.spi.transfer(&mut addr_buf) {
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Ok(_) => self.spi.transfer(reg_data),
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Err(e) => Err(e),
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};
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let result = match (result, checksum) {
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(Ok(_),None) =>
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Ok(None),
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(Ok(_), Some(checksum_out)) => {
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let mut checksum_buf = [checksum_out; 1];
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match self.spi.transfer(&mut checksum_buf) {
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Ok(_) => Ok(Some(checksum_buf[0])),
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Err(e) => Err(e),
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}
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}
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(Err(e), _) =>
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Err(e),
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};
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let _ = self.nss.set_high();
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result
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}
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}
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150
firmware/src/ad7172/adc.rs
Normal file
150
firmware/src/ad7172/adc.rs
Normal file
@ -0,0 +1,150 @@
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::blocking::spi::Transfer;
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use super::checksum::{ChecksumMode, Checksum};
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use super::AdcError;
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use super::regs::*;
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/// AD7172-2 implementation
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///
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/// [Manual](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf)
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pub struct Adc<SPI: Transfer<u8>, NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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checksum_mode: ChecksumMode,
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}
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impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
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pub fn new(spi: SPI, mut nss: NSS) -> Result<Self, SPI::Error> {
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let _ = nss.set_high();
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let mut adc = Adc {
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spi, nss,
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checksum_mode: ChecksumMode::Off,
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};
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adc.reset()?;
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Ok(adc)
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}
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/// `0x00DX` for AD7271-2
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pub fn identify(&mut self) -> Result<u16, AdcError<SPI::Error>> {
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self.read_reg(&Id)
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.map(|id| id.id())
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}
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pub fn set_checksum_mode(&mut self, mode: ChecksumMode) -> Result<(), AdcError<SPI::Error>> {
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let mut ifmode = self.read_reg(&IfMode)?;
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ifmode.set_crc(mode);
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self.checksum_mode = mode;
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self.write_reg(&IfMode, &mut ifmode)?;
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Ok(())
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}
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// pub fn setup(&mut self) -> Result<(), SPI::Error> {
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// let mut buf = [0, 0, 0];
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// adc.write_reg(Register::AdcMode, &mut buf)?;
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// let mut buf = [0, 1, 0];
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// adc.write_reg(Register::IfMode, &mut buf)?;
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// let mut buf = [0, 0, 0];
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// adc.write_reg(Register::GpioCon, &mut buf)?;
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// Ok(())
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// }
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/// Returns the channel the data is from
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pub fn data_ready(&mut self) -> Result<Option<u8>, AdcError<SPI::Error>> {
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self.read_reg(&Status)
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.map(|status| {
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if status.ready() {
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Some(status.channel())
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} else {
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None
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}
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})
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}
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/// Get data
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pub fn read_data(&mut self) -> Result<u32, AdcError<SPI::Error>> {
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self.read_reg(&Data)
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.map(|data| data.data())
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}
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fn read_reg<R: Register>(&mut self, reg: &R) -> Result<R::Data, AdcError<SPI::Error>> {
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let mut reg_data = R::Data::empty();
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let address = 0x40 | reg.address();
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let mut checksum = Checksum::new(self.checksum_mode);
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checksum.feed(address);
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let checksum_out = checksum.result();
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let checksum_in = self.transfer(address, reg_data.as_mut(), checksum_out)?;
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for &mut b in reg_data.as_mut() {
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checksum.feed(b);
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}
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let checksum_expected = checksum.result();
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if checksum_expected != checksum_in {
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return Err(AdcError::ChecksumMismatch(checksum_expected, checksum_in));
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}
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Ok(reg_data)
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}
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fn write_reg<R: Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), AdcError<SPI::Error>> {
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let address = reg.address();
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let mut checksum = Checksum::new(match self.checksum_mode {
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ChecksumMode::Off => ChecksumMode::Off,
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// write checksums are always crc
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ChecksumMode::Xor => ChecksumMode::Crc,
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ChecksumMode::Crc => ChecksumMode::Crc,
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});
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checksum.feed(address);
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for &mut b in reg_data.as_mut() {
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checksum.feed(b);
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}
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let checksum_out = checksum.result();
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self.transfer(address, reg_data.as_mut(), checksum_out)?;
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Ok(())
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}
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fn update_reg<R, F, A>(&mut self, reg: &R, f: F) -> Result<A, AdcError<SPI::Error>>
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where
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R: Register,
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F: FnOnce(&mut R::Data) -> A,
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{
|
||||
let mut reg_data = self.read_reg(reg)?;
|
||||
let result = f(&mut reg_data);
|
||||
self.write_reg(reg, &mut reg_data)?;
|
||||
Ok(result)
|
||||
}
|
||||
|
||||
pub fn reset(&mut self) -> Result<(), SPI::Error> {
|
||||
let mut buf = [0xFFu8; 8];
|
||||
let _ = self.nss.set_low();
|
||||
let result = self.spi.transfer(&mut buf);
|
||||
let _ = self.nss.set_high();
|
||||
result?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn transfer<'w>(&mut self, addr: u8, reg_data: &'w mut [u8], checksum: Option<u8>) -> Result<Option<u8>, SPI::Error> {
|
||||
let mut addr_buf = [addr];
|
||||
|
||||
let _ = self.nss.set_low();
|
||||
let result = match self.spi.transfer(&mut addr_buf) {
|
||||
Ok(_) => self.spi.transfer(reg_data),
|
||||
Err(e) => Err(e),
|
||||
};
|
||||
let result = match (result, checksum) {
|
||||
(Ok(_),None) =>
|
||||
Ok(None),
|
||||
(Ok(_), Some(checksum_out)) => {
|
||||
let mut checksum_buf = [checksum_out; 1];
|
||||
match self.spi.transfer(&mut checksum_buf) {
|
||||
Ok(_) => Ok(Some(checksum_buf[0])),
|
||||
Err(e) => Err(e),
|
||||
}
|
||||
}
|
||||
(Err(e), _) =>
|
||||
Err(e),
|
||||
};
|
||||
let _ = self.nss.set_high();
|
||||
|
||||
result
|
||||
}
|
||||
}
|
||||
44
firmware/src/ad7172/checksum.rs
Normal file
44
firmware/src/ad7172/checksum.rs
Normal file
@ -0,0 +1,44 @@
|
||||
#[derive(Clone, Copy, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum ChecksumMode {
|
||||
Off = 0b00,
|
||||
/// Seems much less reliable than `Crc`
|
||||
Xor = 0b01,
|
||||
Crc = 0b10,
|
||||
}
|
||||
|
||||
pub struct Checksum {
|
||||
mode: ChecksumMode,
|
||||
state: u8,
|
||||
}
|
||||
|
||||
impl Checksum {
|
||||
pub fn new(mode: ChecksumMode) -> Self {
|
||||
Checksum { mode, state: 0 }
|
||||
}
|
||||
|
||||
pub fn feed(&mut self, input: u8) {
|
||||
match self.mode {
|
||||
ChecksumMode::Off => {},
|
||||
ChecksumMode::Xor => self.state ^= input,
|
||||
ChecksumMode::Crc => {
|
||||
for i in 0..8 {
|
||||
let input_mask = 0x80 >> i;
|
||||
self.state = (self.state << 1) ^
|
||||
if ((self.state & 0x80) != 0) != ((input & input_mask) != 0) {
|
||||
0x07 /* x8 + x2 + x + 1 */
|
||||
} else {
|
||||
0
|
||||
};
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn result(&self) -> Option<u8> {
|
||||
match self.mode {
|
||||
ChecksumMode::Off => None,
|
||||
_ => Some(self.state)
|
||||
}
|
||||
}
|
||||
}
|
||||
32
firmware/src/ad7172/mod.rs
Normal file
32
firmware/src/ad7172/mod.rs
Normal file
@ -0,0 +1,32 @@
|
||||
mod regs;
|
||||
mod checksum;
|
||||
pub use checksum::ChecksumMode;
|
||||
mod adc;
|
||||
pub use adc::*;
|
||||
|
||||
#[repr(u8)]
|
||||
pub enum Input {
|
||||
Ain0 = 0,
|
||||
Ain1 = 1,
|
||||
Ain2 = 2,
|
||||
Ain3 = 3,
|
||||
Ain4 = 4,
|
||||
TemperaturePos = 17,
|
||||
TemperatureNeg = 18,
|
||||
AnalogSupplyPos = 19,
|
||||
AnalogSupplyNeg = 20,
|
||||
RefPos = 21,
|
||||
RefNeg = 22,
|
||||
}
|
||||
|
||||
#[derive(Clone, Debug, PartialEq)]
|
||||
pub enum AdcError<SPI> {
|
||||
SPI(SPI),
|
||||
ChecksumMismatch(Option<u8>, Option<u8>),
|
||||
}
|
||||
|
||||
impl<SPI> From<SPI> for AdcError<SPI> {
|
||||
fn from(e: SPI) -> Self {
|
||||
AdcError::SPI(e)
|
||||
}
|
||||
}
|
||||
152
firmware/src/ad7172/regs.rs
Normal file
152
firmware/src/ad7172/regs.rs
Normal file
@ -0,0 +1,152 @@
|
||||
use byteorder::{BigEndian, ByteOrder};
|
||||
use bit_field::BitField;
|
||||
|
||||
use super::*;
|
||||
|
||||
pub trait Register {
|
||||
type Data: RegisterData;
|
||||
fn address(&self) -> u8;
|
||||
}
|
||||
pub trait RegisterData {
|
||||
fn empty() -> Self;
|
||||
fn as_mut(&mut self) -> &mut [u8];
|
||||
}
|
||||
|
||||
macro_rules! def_reg {
|
||||
($Reg: ident, $reg: ident, $addr: expr, $size: expr) => {
|
||||
pub struct $Reg;
|
||||
impl Register for $Reg {
|
||||
type Data = $reg::Data;
|
||||
fn address(&self) -> u8 {
|
||||
$addr
|
||||
}
|
||||
}
|
||||
mod $reg {
|
||||
pub struct Data(pub [u8; $size]);
|
||||
impl super::RegisterData for Data {
|
||||
fn empty() -> Self {
|
||||
Data([0; $size])
|
||||
}
|
||||
fn as_mut(&mut self) -> &mut [u8] {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
($Reg: ident, $index: ty, $reg: ident, $addr: expr, $size: expr) => {
|
||||
struct $Reg { pub index: $index, }
|
||||
impl Register for $Reg {
|
||||
type Data = $reg::Data;
|
||||
fn address(&self) -> u8 {
|
||||
$addr + (self.index as u8)
|
||||
}
|
||||
}
|
||||
mod $reg {
|
||||
pub struct Data(pub [u8; $size]);
|
||||
impl super::RegisterData for Data {
|
||||
fn empty() -> Self {
|
||||
Data([0; $size])
|
||||
}
|
||||
fn as_mut(&mut self) -> &mut [u8] {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(Status, status, 0x00, 1);
|
||||
impl status::Data {
|
||||
/// Is there new data to read?
|
||||
pub fn ready(&self) -> bool {
|
||||
! self.0[0].get_bit(7)
|
||||
}
|
||||
|
||||
/// Channel for which data is ready
|
||||
pub fn channel(&self) -> u8 {
|
||||
self.0[0].get_bits(0..=1)
|
||||
}
|
||||
|
||||
pub fn adc_error(&self) -> bool {
|
||||
self.0[0].get_bit(6)
|
||||
}
|
||||
|
||||
pub fn crc_error(&self) -> bool {
|
||||
self.0[0].get_bit(5)
|
||||
}
|
||||
|
||||
pub fn reg_error(&self) -> bool {
|
||||
self.0[0].get_bit(4)
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(IfMode, if_mode, 0x02, 2);
|
||||
impl if_mode::Data {
|
||||
pub fn set_crc(&mut self, mode: ChecksumMode) {
|
||||
self.0[1].set_bits(2..=3, mode as u8);
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(Data, data, 0x04, 3);
|
||||
impl data::Data {
|
||||
pub fn data(&self) -> u32 {
|
||||
(u32::from(self.0[0]) << 16) |
|
||||
(u32::from(self.0[1]) << 8) |
|
||||
u32::from(self.0[2])
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(Id, id, 0x07, 2);
|
||||
impl id::Data {
|
||||
pub fn id(&self) -> u16 {
|
||||
BigEndian::read_u16(&self.0)
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(Channel, u8, channel, 0x10, 2);
|
||||
impl channel::Data {
|
||||
pub fn enabled(&self) -> bool {
|
||||
self.0[0].get_bit(7)
|
||||
}
|
||||
|
||||
pub fn set_enabled(&mut self, value: bool) {
|
||||
self.0[0].set_bit(7, value);
|
||||
}
|
||||
}
|
||||
|
||||
def_reg!(SetupCon, u8, setup_con, 0x20, 2);
|
||||
|
||||
def_reg!(FiltCon, u8, filt_con, 0x80, 2);
|
||||
|
||||
// #[allow(unused)]
|
||||
// #[derive(Clone, Copy)]
|
||||
// #[repr(u8)]
|
||||
// pub enum Register {
|
||||
// Status = 0x00,
|
||||
// AdcMode = 0x01,
|
||||
// IfMode = 0x02,
|
||||
// RegCheck = 0x03,
|
||||
// Data = 0x04,
|
||||
// GpioCon = 0x06,
|
||||
// Id = 0x07,
|
||||
// Ch0 = 0x10,
|
||||
// Ch1 = 0x11,
|
||||
// Ch2 = 0x12,
|
||||
// Ch3 = 0x13,
|
||||
// SetupCon0 = 0x20,
|
||||
// SetupCon1 = 0x21,
|
||||
// SetupCon2 = 0x22,
|
||||
// SetupCon3 = 0x23,
|
||||
// FiltCon0 = 0x28,
|
||||
// FiltCon1 = 0x29,
|
||||
// FiltCon2 = 0x2A,
|
||||
// FiltCon3 = 0x2B,
|
||||
// Offset0 = 0x30,
|
||||
// Offset1 = 0x31,
|
||||
// Offset2 = 0x32,
|
||||
// Offset3 = 0x33,
|
||||
// Gain0 = 0x38,
|
||||
// Gain1 = 0x39,
|
||||
// Gain2 = 0x3A,
|
||||
// Gain3 = 0x3B,
|
||||
// }
|
||||
Loading…
Reference in New Issue
Block a user