add ethmac driver
Alexander Shafir
parent
c03b6a6fb7
commit
0ab3b6116e
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@ -0,0 +1,446 @@
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use cortex_m;
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use tm4c129x;
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use core::slice;
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use smoltcp::Error;
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use smoltcp::phy::{DeviceLimits, Device};
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use smoltcp::wire::{EthernetAddress};
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const EPHY_BMCR: u8 = 0x00; // Ethernet PHY Basic Mode Control
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const EPHY_BMSR: u8 = 0x01; // Ethernet PHY Basic Mode Status
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const EPHY_ID1: u8 = 0x02; // Ethernet PHY Identifier Register 1
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const EPHY_ID2: u8 = 0x03; // Ethernet PHY Identifier Register 2
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const EPHY_REGCTL: u8 = 0x0D; // Ethernet PHY Register Control
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const EPHY_ADDAR: u8 = 0x0E; // Ethernet PHY Address or Data
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const EPHY_LEDCFG: u8 = 0x25; // Ethernet PHY LED Configuration
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// Transmit DMA descriptor flags
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const EMAC_TDES0_OWN: u32 = 0x80000000; // Indicates that the descriptor is owned by the DMA
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const EMAC_TDES0_LS: u32 = 0x20000000; // Last Segment
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const EMAC_TDES0_FS: u32 = 0x10000000; // First Segment
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const EMAC_TDES0_TCH: u32 = 0x00100000; // Second Address Chained
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const EMAC_TDES1_TBS1: u32 = 0x00001FFF; // Transmit Buffer 1 Size
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// Receive DMA descriptor flags
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const EMAC_RDES0_OWN: u32 = 0x80000000; // indicates that the descriptor is owned by the DMA
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const EMAC_RDES0_FL: u32 = 0x3FFF0000; // Frame Length
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const EMAC_RDES0_ES: u32 = 0x00008000; // Error Summary
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const EMAC_RDES1_RCH: u32 = 0x00004000; // Second Address Chained
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const EMAC_RDES1_RBS1: u32 = 0x00001FFF; // Receive Buffer 1 Size
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const EMAC_RDES0_FS: u32 = 0x00000200; // First Descriptor
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const EMAC_RDES0_LS: u32 = 0x00000100; // Last Descriptor
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const ETH_DESC_U32_SIZE: usize = 8;
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const ETH_TX_BUFFER_COUNT: usize = 2;
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const ETH_TX_BUFFER_SIZE: usize = 1536;
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const ETH_RX_BUFFER_COUNT: usize = 3;
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const ETH_RX_BUFFER_SIZE: usize = 1536;
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pub struct EmacData {
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pub tx_desc_buf: [u32; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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pub rx_desc_buf: [u32; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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pub tx_cur_desc: usize,
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pub rx_cur_desc: usize,
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pub tx_counter: u32,
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pub rx_counter: u32,
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pub tx_pkt_buf: [u8; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
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pub rx_pkt_buf: [u8; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
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}
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static mut EMAC_DATA: EmacData = EmacData {
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tx_desc_buf: [0; ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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rx_desc_buf: [0; ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE],
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tx_cur_desc: 0,
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rx_cur_desc: 0,
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tx_counter: 0,
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rx_counter: 0,
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tx_pkt_buf: [0; ETH_TX_BUFFER_COUNT * ETH_TX_BUFFER_SIZE],
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rx_pkt_buf: [0; ETH_RX_BUFFER_COUNT * ETH_RX_BUFFER_SIZE],
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};
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pub fn delay(d: i32) {
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for x in 0..d {
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unsafe {
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asm!("
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NOP
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");
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}
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}
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}
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fn phy_read(reg_addr: u8) -> u16 {
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unsafe {
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let emac0 = tm4c129x::EMAC0.get();
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// Make sure the MII is idle
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while (*emac0).miiaddr.read().miib().bit() {};
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// Tell the MAC to read the given PHY register
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(*emac0).miiaddr.write(|w| {
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w.cr()._100_150()
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.mii().bits(reg_addr & 0x1F)
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.miib().bit(true)
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} );
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// Wait for the read to complete
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while (*emac0).miiaddr.read().miib().bit() {};
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(*emac0).miidata.read().data().bits()
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}
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}
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fn phy_write(reg_addr: u8, reg_data: u16) {
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unsafe {
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let emac0 = tm4c129x::EMAC0.get();
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// Make sure the MII is idle
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while (*emac0).miiaddr.read().miib().bit() {};
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(*emac0).miidata.write(|w| {
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w.data().bits(reg_data)
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} );
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// Tell the MAC to write the given PHY register
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(*emac0).miiaddr.write(|w| {
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w.cr()._100_150()
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.mii().bits(reg_addr & 0x1F)
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.miiw().bit(true)
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.miib().bit(true)
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} );
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// Wait for the read to complete
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while (*emac0).miiaddr.read().miib().bit() {};
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}
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}
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// Writes a value to an extended PHY register in MMD address space
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fn phy_write_ext(reg_addr: u8, reg_data: u16) {
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phy_write(EPHY_REGCTL, 0x001F); // set address (datasheet page 1612)
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phy_write(EPHY_ADDAR, reg_addr as u16);
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phy_write(EPHY_REGCTL, 0x401F); // set write mode
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phy_write(EPHY_ADDAR, reg_data);
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}
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pub fn init(mac_addr: [u8; 6]) {
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cortex_m::interrupt::free(|cs| {
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let sysctl = tm4c129x::SYSCTL.borrow(cs);
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let emac0 = tm4c129x::EMAC0.borrow(cs);
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sysctl.rcgcemac.modify(|_, w| w.r0().bit(true)); // Bring up MAC
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sysctl.sremac.modify(|_, w| w.r0().bit(true)); // Activate MAC reset
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delay(16);
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sysctl.sremac.modify(|_, w| w.r0().bit(false)); // Dectivate MAC reset
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sysctl.rcgcephy.modify(|_, w| w.r0().bit(true)); // Bring up PHY
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sysctl.srephy.modify(|_, w| w.r0().bit(true)); // Activate PHY reset
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delay(16);
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sysctl.srephy.modify(|_, w| w.r0().bit(false)); // Dectivate PHY reset
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while !sysctl.premac.read().r0().bit() {} // Wait for the MAC to come out of reset
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while !sysctl.prephy.read().r0().bit() {} // Wait for the PHY to come out of reset
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delay(10000);
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emac0.dmabusmod.modify(|_, w| w.swr().bit(true)); // Reset MAC DMA
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while emac0.dmabusmod.read().swr().bit() {} // Wait for the MAC DMA to come out of reset
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delay(1000);
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emac0.miiaddr.write(|w| w.cr()._100_150()); // Set the MII CSR clock speed.
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// Checking PHY
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if (phy_read(EPHY_ID1) != 0x2000) | (phy_read(EPHY_ID2) != 0xA221) { // TM4C1294 PHY IDs
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panic!("PHY ID error!");
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}
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// Reset PHY transceiver
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phy_write(EPHY_BMCR, 1); // Initiate MII reset
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while 1 == (phy_read(EPHY_BMCR) & 1) {}; // Wait for the reset to be completed
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// Configure PHY LEDs
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phy_write_ext(EPHY_LEDCFG, 0x0008); //LED0 Link OK/Blink on TX/RX Activit
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// Tell the PHY to start an auto-negotiation cycle
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phy_write(EPHY_BMCR, 0b00010010_00000000); //ANEN and RESTARTAN
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// Set the DMA operation mode
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emac0.dmaopmode.write(|w|
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w.rsf().bit(true) // Receive Store and Forward
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.tsf().bit(true) // Transmit Store and Forward
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.ttc()._64() // Transmit Threshold Control
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.rtc()._64() // Receive Threshold Control
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);
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// Set the bus mode register.
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emac0.dmabusmod.write(|w| unsafe {
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w.atds().bit(true)
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.aal().bit(true) // Address Aligned Beats
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.usp().bit(true) // Use Separate Programmable Burst Length ???
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.rpbl().bits(1) // RX DMA Programmable Burst Length
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.pbl().bits(1) // Programmable Burst Length
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.pr().bits(0) // Priority Ratio 1:1
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});
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// Disable all the MMC interrupts as these are enabled by default at reset.
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emac0.mmcrxim.write(|w| unsafe { w.bits(0xFFFFFFFF)});
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emac0.mmctxim.write(|w| unsafe { w.bits(0xFFFFFFFF)});
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// Set MAC configuration options
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emac0.cfg.write(|w|
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w.dupm().bit(true) // MAC operates in full-duplex mode
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.ipc().bit(true) // Checksum Offload Enable
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.prelen()._7() // 7 bytes of preamble
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.ifg()._96() // 96 bit times
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.bl()._1024() // Back-Off Limit 1024
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.ps().bit(true) // ?
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);
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// Set the maximum receive frame size
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emac0.wdogto.write(|w| unsafe {
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w.bits(0) // ??? no use watchdog
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});
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// Set the high 2 bytes of the MAC address
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emac0.addr0h.write(|w| unsafe { w.addrhi().bits(mac_addr[4] as u16 | ((mac_addr[5] as u16) << 8)) });
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// Set the low 4 bytes of the MAC address
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emac0.addr0l.write(|w| unsafe {
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w.addrlo().bits(mac_addr[0] as u32 | ((mac_addr[1] as u32) << 8) | ((mac_addr[2] as u32) << 16) | ((mac_addr[3] as u32) << 24))
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} );
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// Set MAC filtering options (?)
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emac0.framefltr.write(|w|
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w.hpf().bit(true) // Hash or Perfect Filter
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// .hmc().bit(true) // Hash Multicast ???
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.pm().bit(true) // Pass All Multicast
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);
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// Initialize hash table
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emac0.hashtbll.write(|w| unsafe { w.htl().bits(0 as u32)});
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emac0.hashtblh.write(|w| unsafe { w.hth().bits(0 as u32)});
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emac0.flowctl.write(|w| unsafe { w.bits(0)}); // Disable flow control ???
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// Initialize TX DMA descriptors
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for x in 0..ETH_TX_BUFFER_COUNT {
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let p = x * ETH_DESC_U32_SIZE;
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let r = x * ETH_TX_BUFFER_SIZE;
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unsafe {
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// Initialize transmit flags
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EMAC_DATA.tx_desc_buf[p + 0] = 0;
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// Initialize transmit buffer size
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EMAC_DATA.tx_desc_buf[p + 1] = 0;
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// Transmit buffer address
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EMAC_DATA.tx_desc_buf[p + 2] = (&EMAC_DATA.tx_pkt_buf[r] as *const u8) as u32;
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// Next descriptor address
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if x != ETH_TX_BUFFER_COUNT - 1 {
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EMAC_DATA.tx_desc_buf[p + 3] = (&EMAC_DATA.tx_desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
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} else {
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EMAC_DATA.tx_desc_buf[p + 3] = (&EMAC_DATA.tx_desc_buf[0] as *const u32) as u32;
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}
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// Reserved fields
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EMAC_DATA.tx_desc_buf[p + 4] = 0;
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EMAC_DATA.tx_desc_buf[p + 5] = 0;
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// Transmit frame time stamp
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EMAC_DATA.tx_desc_buf[p + 6] = 0;
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EMAC_DATA.tx_desc_buf[p + 7] = 0;
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}
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}
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// Initialize RX DMA descriptors
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for x in 0..ETH_RX_BUFFER_COUNT {
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let p = x * ETH_DESC_U32_SIZE;
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let r = x * ETH_RX_BUFFER_SIZE;
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unsafe {
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// The descriptor is initially owned by the DMA
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EMAC_DATA.rx_desc_buf[p + 0] = EMAC_RDES0_OWN;
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// Use chain structure rather than ring structure
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EMAC_DATA.rx_desc_buf[p + 1] = EMAC_RDES1_RCH | ((ETH_RX_BUFFER_SIZE as u32) & EMAC_RDES1_RBS1);
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// Receive buffer address
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EMAC_DATA.rx_desc_buf[p + 2] = (&EMAC_DATA.rx_pkt_buf[r] as *const u8) as u32;
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// Next descriptor address
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if x != ETH_RX_BUFFER_COUNT - 1 {
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EMAC_DATA.rx_desc_buf[p + 3] = (&EMAC_DATA.rx_desc_buf[p + ETH_DESC_U32_SIZE] as *const u32) as u32;
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} else {
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EMAC_DATA.rx_desc_buf[p + 3] = (&EMAC_DATA.rx_desc_buf[0] as *const u32) as u32;
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}
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// Extended status
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EMAC_DATA.rx_desc_buf[p + 4] = 0;
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// Reserved field
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EMAC_DATA.rx_desc_buf[p + 5] = 0;
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// Transmit frame time stamp
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EMAC_DATA.rx_desc_buf[p + 6] = 0;
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EMAC_DATA.rx_desc_buf[p + 7] = 0;
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}
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}
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unsafe {
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EMAC_DATA.tx_cur_desc = 0;
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EMAC_DATA.rx_cur_desc = 0;
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}
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emac0.txdladdr.write(|w| unsafe { w.bits((&EMAC_DATA.tx_desc_buf[0] as *const u32) as u32)});
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emac0.rxdladdr.write(|w| unsafe { w.bits((&EMAC_DATA.rx_desc_buf[0] as *const u32) as u32)});
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// Manage MAC transmission and reception
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emac0.cfg.modify(|_, w|
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w.re().bit(true) // Receiver Enable
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.te().bit(true) // Transmiter Enable
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);
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// Manage DMA transmission and reception
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emac0.dmaopmode.modify(|_, w|
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w.sr().bit(true) // Start Receive
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.st().bit(true) // Start Transmit
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);
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println!("EMAC init done");
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});
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}
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pub fn info() {
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unsafe {
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static mut BMSR1: u16 = 0;
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static mut R1: u32 = 0;
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// Display EMAC status(es) if need
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let emac0 = tm4c129x::EMAC0.get();
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// let r = (*emac0).dmaris.read().bits();
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let r = 0;
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if R1 != r {
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println!("R=0x{:08x}", r);
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}
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R1 = r;
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// Display PHY/media status
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let bmsr = phy_read(EPHY_BMSR);
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if BMSR1 != bmsr {
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println!("PHY BMSR=0x{:04x}", bmsr);
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}
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BMSR1 = bmsr;
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// Display packets count
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let rxp = EMAC_DATA.rx_counter;
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EMAC_DATA.rx_counter = 0;
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let txp = EMAC_DATA.tx_counter;
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EMAC_DATA.tx_counter = 0;
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if (0 != rxp) || (0 != txp) {
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println!("RX_PKT={} TX_PKT={}", rxp, txp);
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}
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}
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}
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fn release_rx_buf() {
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unsafe {
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EMAC_DATA.rx_cur_desc += ETH_DESC_U32_SIZE;
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if EMAC_DATA.rx_cur_desc >= (ETH_RX_BUFFER_COUNT * ETH_DESC_U32_SIZE) {
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EMAC_DATA.rx_cur_desc = 0;
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}
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EMAC_DATA.rx_desc_buf[EMAC_DATA.rx_cur_desc + 0] = EMAC_RDES0_OWN; // release descriptor
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}
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}
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pub struct EthernetDevice;
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impl Device for EthernetDevice {
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type RxBuffer = RxBuffer;
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type TxBuffer = TxBuffer;
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fn limits(&self) -> DeviceLimits {
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let mut limits = DeviceLimits::default();
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limits.max_transmission_unit = 1500;
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limits.max_burst_size = Some(ETH_RX_BUFFER_COUNT);
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limits
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}
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fn receive(&mut self) -> Result<Self::RxBuffer, Error> {
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unsafe {
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if 0 == (EMAC_DATA.rx_desc_buf[EMAC_DATA.rx_cur_desc + 0] & EMAC_RDES0_OWN) {
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// check for the whole packet in the buffer and no any error
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if (EMAC_RDES0_FS | EMAC_RDES0_LS) == EMAC_DATA.rx_desc_buf[EMAC_DATA.rx_cur_desc + 0] & (EMAC_RDES0_FS | EMAC_RDES0_LS | EMAC_RDES0_ES) {
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// Retrieve the length of the frame
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let mut n = (EMAC_DATA.rx_desc_buf[EMAC_DATA.rx_cur_desc + 0] & EMAC_RDES0_FL) >> 16;
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// Limit the number of data to read
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if n > ETH_RX_BUFFER_SIZE as u32 { n = ETH_RX_BUFFER_SIZE as u32; }
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Ok(RxBuffer(slice::from_raw_parts(EMAC_DATA.rx_desc_buf[EMAC_DATA.rx_cur_desc + 2] as * mut u8,
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n as usize)))
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} else {
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// Ignore invalid frame
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release_rx_buf();
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Err(Error::Exhausted)
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}
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} else {
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Err(Error::Exhausted) // currently no bufferes to process
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}
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}
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}
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fn transmit(&mut self, length: usize) -> Result<Self::TxBuffer, Error> {
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unsafe {
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// Check if the TX DMA buffer released
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if 0 == (EMAC_DATA.tx_desc_buf[EMAC_DATA.tx_cur_desc + 0] & EMAC_TDES0_OWN) {
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// Write the number of bytes to send
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EMAC_DATA.tx_desc_buf[EMAC_DATA.tx_cur_desc + 1] = length as u32 & EMAC_TDES1_TBS1;
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Ok(TxBuffer(slice::from_raw_parts_mut(EMAC_DATA.tx_desc_buf[EMAC_DATA.tx_cur_desc + 2] as * mut u8,
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ETH_TX_BUFFER_SIZE)))
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} else {
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// to do if need: Instruct the DMA to poll the receive descriptor list
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Err(Error::Exhausted)
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}
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}
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}
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}
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pub struct RxBuffer(&'static [u8]);
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impl AsRef<[u8]> for RxBuffer {
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fn as_ref(&self) -> &[u8] { self.0 }
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}
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impl Drop for RxBuffer {
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fn drop(&mut self) {
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release_rx_buf();
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unsafe { EMAC_DATA.rx_counter += 1 }; // Increment RX statistics
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}
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||||
}
|
||||
|
||||
pub struct TxBuffer(&'static mut [u8]);
|
||||
|
||||
impl AsRef<[u8]> for TxBuffer {
|
||||
fn as_ref(&self) -> &[u8] { self.0 }
|
||||
}
|
||||
|
||||
impl AsMut<[u8]> for TxBuffer {
|
||||
fn as_mut(&mut self) -> &mut [u8] { self.0 }
|
||||
}
|
||||
|
||||
impl Drop for TxBuffer {
|
||||
fn drop(&mut self) {
|
||||
unsafe {
|
||||
// Use chain structure rather than ring structure
|
||||
// Set LS and FS flags as the data fits in a single buffer and give the ownership of the descriptor to the DMA
|
||||
EMAC_DATA.tx_desc_buf[EMAC_DATA.tx_cur_desc + 0] = EMAC_TDES0_LS | EMAC_TDES0_FS | EMAC_TDES0_TCH;
|
||||
EMAC_DATA.tx_desc_buf[EMAC_DATA.tx_cur_desc + 0] |= EMAC_TDES0_OWN; // Set ownersip for DMA here
|
||||
|
||||
cortex_m::interrupt::free(|cs| {
|
||||
let emac0 = tm4c129x::EMAC0.borrow(cs);
|
||||
// Clear TU flag to resume processing
|
||||
emac0.dmaris.write(|w| w.tu().bit(true));
|
||||
// Instruct the DMA to poll the transmit descriptor list
|
||||
emac0.txpolld.write(|w| w.tpd().bits(0));
|
||||
});
|
||||
|
||||
// Calculate next DMA descriptor offset
|
||||
let mut tx_next_desc = EMAC_DATA.tx_cur_desc + ETH_DESC_U32_SIZE;
|
||||
if tx_next_desc >= (ETH_TX_BUFFER_COUNT * ETH_DESC_U32_SIZE) {
|
||||
tx_next_desc = 0;
|
||||
}
|
||||
EMAC_DATA.tx_cur_desc = tx_next_desc;
|
||||
|
||||
EMAC_DATA.tx_counter += 1; // Increment RX statistics
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue