2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 19:28:26 +08:00
Commit Graph

4484 Commits

Author SHA1 Message Date
fed24309b8 pdq: documentation 2017-05-02 18:55:02 +02:00
1a1edb13bf pdq2 -> pdq 2017-05-02 18:05:41 +02:00
534e681d0b pdq2: use 16 bit data, buffered read_mem() 2017-04-13 20:49:46 +02:00
90cf11994e spi: style 2017-04-13 13:38:29 +02:00
8446cccb4e pdq2: mem_read 2017-04-13 13:38:13 +02:00
20652ce128 pdq2: align subsequent writes to end 2017-04-09 13:50:19 +02:00
ed8edf318d sma_spi: undo cri_con 2017-04-08 17:19:35 +02:00
78dd4b8614 pdq2: memory write, kernel_invariants 2017-04-08 17:16:19 +02:00
16b7f8f50c sma_spi: cri/cd changes 2017-04-08 17:16:19 +02:00
1e6e81a19e sma_spi: LVCMOS25 2017-04-08 17:16:19 +02:00
0838981bed coredevice.spi: kernel invariants and style 2017-04-08 17:16:19 +02:00
555b3c38c1 sma_spi: free up user_sma pins 2017-04-08 17:16:19 +02:00
2c7c6143ab sma_spi: add demo target with SPI on four SMA 2017-04-08 17:16:19 +02:00
f13f6eb7be pdq2: memory write 2017-04-08 17:16:19 +02:00
b9c61ae2da pdq2: crc/frame register accessors 2017-04-08 17:16:19 +02:00
1ce1b7cd71 doc: pdq2 spi backend 2017-04-08 17:16:19 +02:00
aebbaa339e pdq2: config writes 2017-04-08 17:16:18 +02:00
1ee3f96482 test: self.break_realtime → self.core.break_realtime 2017-03-27 16:31:11 +08:00
whitequark
ac9e8b8568 test: avoid underflow in DMA replay test. 2017-03-17 12:09:02 +00:00
whitequark
dbea679e96 Revert "test: relax test_rpc_timing on Windows."
This reverts commit e9cf451c0b.
2017-03-17 11:34:45 +00:00
whitequark
e9cf451c0b test: relax test_rpc_timing on Windows. 2017-03-17 11:20:16 +00:00
whitequark
7dc7dcda2c test: relax test_pulse_rate_dds to only catch catastrophic slowdown. 2017-03-17 11:17:47 +00:00
whitequark
4de336fbe9 gateware: reverse bytes of SDRAM word, not bits. 2017-03-17 11:16:46 +00:00
whitequark
6b63322106 gateware: reverse SDRAM words in RTIO DMA engine. 2017-03-17 07:29:28 +00:00
whitequark
4b14887ddb gateware: work around ISE/Vivado bugs with very wide shifts. 2017-03-17 07:29:28 +00:00
f5aa73b8fa satman: unbreak after c586035c 2017-03-15 17:26:09 +08:00
whitequark
c586035caa runtime: add an option to reboot after a panic. 2017-03-14 09:02:28 +00:00
whitequark
80c75ed505 firmware: fix for unwinder update. 2017-03-14 08:50:32 +00:00
whitequark
618942bda6 conda: bump misoc. 2017-03-14 08:35:04 +00:00
whitequark
4beda73217 firmware: don't build libdyld through misoc. 2017-03-14 08:33:31 +00:00
a7de58b604 rtio: Inout → InOut 2017-03-14 14:18:55 +08:00
13ae1d1a38 drtio: input unittest 2017-03-14 14:14:55 +08:00
56fd9b3b4b drtio: input fixes 2017-03-14 14:14:43 +08:00
856a64f6d2 drtio: use TTLInOut in device_db 2017-03-14 14:13:52 +08:00
95ede18809 drtio: support PHY latency compensation 2017-03-14 00:01:38 +08:00
497c795d8c drtio: input support (untested) 2017-03-13 23:54:44 +08:00
d1b9f9d737 drtio: rt_packets → rt_packet 2017-03-13 00:10:07 +08:00
6b7c781ff2 drtio: introduce 'standard request' interface in RT packet layer 2017-03-13 00:08:03 +08:00
2b8729f326 drtio: clear any read request on satellite reset 2017-03-13 00:00:38 +08:00
1dbfaf5ad0 Revert "conda: bump misoc (pcu/ISE fix)"
This reverts commit d5d3e25f97.
2017-03-08 23:15:23 +01:00
0c959ba6ea Revert "conda: actually bump misoc (pcu/ISE fix)"
This reverts commit ccc4cf8a22.
2017-03-08 23:15:21 +01:00
ccc4cf8a22 conda: actually bump misoc (pcu/ISE fix) 2017-03-08 17:34:38 +01:00
d5d3e25f97 conda: bump misoc (pcu/ISE fix) 2017-03-08 17:32:59 +01:00
whitequark
b391598c87 artiq_devtool: add reset action. 2017-03-07 14:37:08 +00:00
whitequark
5bbb05362b runtime: update smoltcp. 2017-03-07 11:36:28 +00:00
whitequark
d52723d5bc runtime: allow setting log level in configuration. 2017-03-07 11:36:28 +00:00
whitequark
cce1481fac artiq_devtool: add hotswap action. 2017-03-07 11:36:28 +00:00
whitequark
795a3e24d8 artiq_coreboot: block until hotswap image is actually received. 2017-03-07 11:36:28 +00:00
804e69b144 language: add "W" (Watt) to units 2017-03-07 10:03:42 +08:00
6895236794 frontend: fix permissions 2017-03-07 00:47:45 +08:00