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pdq2: config writes
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from artiq.language.core import (kernel, portable, delay_mu, delay)
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from artiq.language.units import ns, us
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from artiq.coredevice import spi
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_PDQ2_SPI_CONFIG = (
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0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX
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)
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@portable
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def _PDQ2_CMD(board, is_mem, adr, we):
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return (adr << 0) | (is_mem << 2) | (board << 3) | (we << 7)
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_PDQ2_ADR_CONFIG = 0
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_PDQ2_ADR_CRC = 1
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_PDQ2_ADR_FRAME = 2
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class PDQ2:
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"""
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:param spi_device: Name of the SPI bus this device is on.
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:param chip_select: Value to drive on the chip select lines
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during transactions.
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"""
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def __init__(self, dmgr, spi_device, chip_select=1):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_device)
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self.chip_select = chip_select
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@kernel
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def setup_bus(self, write_div=4, read_div=15):
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"""Configure the SPI bus and the SPI transaction parameters
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for this device. This method has to be called before any other method
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if the bus has been used to access a different device in the meantime.
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This method advances the timeline by the duration of two
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RTIO-to-Wishbone bus transactions.
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:param write_div: Write clock divider.
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:param read_div: Read clock divider.
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"""
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# write: 4*8ns >= 20ns = 2*clk (clock de-glitching 50MHz)
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# read: 15*8*ns >= ~100ns = 5*clk (clk de-glitching latency + miso
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# latency)
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self.bus.set_config_mu(_PDQ2_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 16, 0)
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@kernel
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def write(self, data):
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"""Write 16 bits of data.
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This method advances the timeline by the duration of the SPI transfer
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and the required CS high time.
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"""
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self.bus.write(data << 16)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@kernel
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def write_config(self, config, board=0xf):
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board &= 0xf
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self.write(
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(_PDQ2_CMD(board, 0, _PDQ2_ADR_CONFIG, 1) << 24) |
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(config << 16)
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)
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