mirror of https://github.com/m-labs/artiq.git
pdq2: memory write, kernel_invariants
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@ -1,5 +1,4 @@
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from artiq.language.core import (kernel, portable, delay_mu, delay)
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from artiq.language.units import ns, us
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from artiq.language.core import kernel, portable, delay_mu
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from artiq.coredevice import spi
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@ -28,6 +27,8 @@ class PDQ2:
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during transactions.
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"""
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kernel_invariants = {"core", "chip_select", "bus"}
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def __init__(self, dmgr, spi_device, chip_select=1):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_device)
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@ -66,7 +67,10 @@ class PDQ2:
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return self.bus.input_async() & 0xff
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@kernel
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def write_config(self, config, board=0xf):
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def write_config(self, reset=0, clk2x=0, enable=1,
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trigger=0, aux_miso=0, aux_dac=0b111, board=0xf):
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config = ((reset << 0) | (clk2x << 1) | (enable << 2) |
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(trigger << 3) | (aux_miso << 4) | (aux_dac << 5))
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self.write_reg(_PDQ2_ADR_CONFIG, config, board)
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@kernel
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@ -97,7 +101,7 @@ class PDQ2:
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delay_mu(3*self.bus.ref_period_mu - self.bus.xfer_period_mu -
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self.bus.write_period_mu)
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self.bus.set_xfer(self.chip_select, 16, 0)
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for i in len(data)//2:
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for i in range(len(data)//2):
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self.bus.write((data[2*i] << 24) | (data[2*i + 1] << 16))
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delay_mu(-self.bus.write_period_mu)
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delay_mu(self.bus.write_period_mu + self.bus.ref_period_mu)
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