mirror of https://github.com/m-labs/artiq.git
pdq2: use 16 bit data, buffered read_mem()
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@ -100,29 +100,32 @@ class PDQ2:
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((adr & 0x00ff) << 16) | (adr & 0xff00))
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delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu)
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self.bus.set_xfer(self.chip_select, 16, 0)
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for i in range(len(data)//2):
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self.bus.write((data[2*i] << 24) | (data[2*i + 1] << 16))
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for i in data:
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self.bus.write(i << 16)
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delay_mu(-self.bus.write_period_mu)
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delay_mu(self.bus.write_period_mu + self.bus.ref_period_mu)
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# get to 20ns min cs high
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@kernel
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def read_mem(self, mem, adr, data, board=0xf):
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def read_mem(self, mem, adr, data, board=0xf, buffer=8):
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n = len(data)
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if not n:
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return
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self.bus.set_xfer(self.chip_select, 24, 8)
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self.bus.write((_PDQ2_CMD(board, 1, mem, 0) << 24) |
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((adr & 0x00ff) << 16) | (adr & 0xff00))
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delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu)
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self.bus.set_xfer(self.chip_select, 0, 16)
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for i in range(len(data)//2):
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for i in range(n):
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self.bus.write(0)
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delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu)
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self.bus.read_async()
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d = self.bus.input_async()
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data[2*i] = (d >> 8) & 0xff
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data[2*i + 1] = d & 0xff
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return int(self.bus.input_async() & 0xff) # FIXME: m-labs/artiq#713
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delay_mu(self.bus.write_period_mu + self.bus.ref_period_mu)
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# get to 20ns min cs high
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delay_mu(-self.bus.write_period_mu)
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if i > 0:
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delay_mu(-3*self.bus.ref_period_mu)
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self.bus.read_async()
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if i > buffer:
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data[i - 1 - buffer] = self.bus.input_async() & 0xffff
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delay_mu(self.bus.write_period_mu)
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self.bus.set_xfer(self.chip_select, 16, 0)
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pass
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self.bus.read_async()
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for i in range(max(0, n - buffer - 1), n):
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data[i] = self.bus.input_async() & 0xffff
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