mirror of https://github.com/m-labs/artiq.git
pdq2: memory write
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@ -51,24 +51,16 @@ class PDQ2:
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self.bus.set_config_mu(_PDQ2_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 16, 0)
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@kernel
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def write(self, data):
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"""Write 16 bits of data.
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This method advances the timeline by the duration of the SPI transfer
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and the required CS high time.
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"""
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self.bus.write(data << 16)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@kernel
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def write_reg(self, adr, data, board):
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self.write((_PDQ2_CMD(board, 0, adr, 1) << 24) | (data << 16))
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self.bus.write((_PDQ2_CMD(board, 0, adr, 1) << 24) | (data << 16))
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@kernel
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def read_reg(self, adr, board):
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self.bus.set_xfer(self.chip_select, 16, 8)
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self.write(_PDQ2_CMD(board, 0, adr, 0) << 24)
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self.bus.write(_PDQ2_CMD(board, 0, adr, 0) << 24)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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self.bus.read_async()
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self.bus.set_xfer(self.chip_select, 16, 0)
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return self.bus.input_async() & 0xff
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@ -99,7 +91,17 @@ class PDQ2:
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@kernel
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def write_mem(self, mem, adr, data, board=0xf):
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pass
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self.bus.set_xfer(self.chip_select, 24, 0)
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self.bus.write((_PDQ2_CMD(board, 1, mem, 1) << 24) |
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((adr & 0x00ff) << 16) | (adr & 0xff00))
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delay_mu(3*self.bus.ref_period_mu - self.bus.xfer_period_mu -
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self.bus.write_period_mu)
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self.bus.set_xfer(self.chip_select, 16, 0)
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for i in len(data)//2:
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self.bus.write((data[2*i] << 24) | (data[2*i + 1] << 16))
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delay_mu(-self.bus.write_period_mu)
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delay_mu(self.bus.write_period_mu + self.bus.ref_period_mu)
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# get to 20ns min cs high
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@kernel
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def read_mem(self, mem, adr, data, board=0xf):
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