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68 Commits

Author SHA1 Message Date
Robert Jördens 2fdc180601 dsp/fir: outputs reset_less (pipelined) 2018-03-13 17:11:50 +00:00
Robert Jördens 2f1029c292 Revert "sawg: advance dds 1/2 by one sample group" 
This reverts commit 8e0a1cbdc8.

c.f. #772

The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
 2017-07-04 17:55:19 +02:00
Robert Jördens 8e0a1cbdc8 sawg: advance dds 1/2 by one sample group 
closes #772
 2017-07-04 16:51:58 +02:00
Robert Jördens 78d1f0fdf6 sawg: fix PhasedAccu resets 2017-07-04 11:56:21 +02:00
Robert Jördens 600a48ac61 dsp.fir: cleanup 2017-06-29 12:18:48 +02:00
Robert Jördens dca662a743 dsp.fir: pipeline final systolic adder 2017-06-29 11:33:19 +02:00
Robert Jördens 32a33500c8 dsp.fir: actively cull zero delays 2017-06-29 11:24:56 +02:00
Robert Jördens f2632e0fd1 sawg: adapt latency to fir changes 
closes #748
 2017-06-28 20:12:30 +02:00
Robert Jördens e7db2c6578 dsp.accu: reset_less outputs 2017-06-28 20:04:58 +02:00
Robert Jördens 6bb994228f dsp.fir: drop x shift 2017-06-28 19:55:15 +02:00
Robert Jördens b9859cc0c3 dsp.fir: remove old/wrong comment 2017-06-28 19:21:57 +02:00
Robert Jördens 55b5b87490 fir: simplify latency compensation 
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
 2017-06-28 19:13:43 +02:00
Robert Jördens d1e5dd334f sawg: use pipeline reset 2017-06-28 19:09:39 +02:00
Robert Jördens 6418205906 dsp.fir: use pipelin-reset 2017-06-28 19:09:21 +02:00
Robert Jördens 07f5e99140 dsp/sat_add: works after previous changes 2017-06-22 18:24:22 +02:00
Robert Jördens 47928a2c0d sawg: disable limiter 
temporary workaround to permit testing other aspects
 2017-06-22 17:31:04 +02:00
Robert Jördens cd2ac53bc5 dsp/sat_add: make width mandatory 2017-06-22 17:28:39 +02:00
Robert Jördens 9b940aa876 dsp/sat_add: spell out logic more 2017-06-22 16:55:13 +02:00
Robert Jördens d0cf0f2b87 sawg/limiter: make signed signals explicitly 2017-06-22 13:44:36 +02:00
Robert Jördens bd1438d28e sawg: wrap limits init values 2017-06-22 10:26:29 +02:00
Robert Jördens cccd01e81e sawg: cleanup sat_add logic 2017-06-22 10:26:29 +02:00
Robert Jördens 570f2cc1ff dsp/tools/SatAdd: fix reuse of clipped signal 2017-06-22 10:26:29 +02:00
Robert Jördens 4b3aad2563 sawg: clean up Config 
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
 2017-06-22 10:26:29 +02:00
Robert Jördens b6569df02f dsp/tools: clean up SatAddMixin logic 2017-06-22 10:26:29 +02:00
Robert Jördens 3f37870e25 sawg: register pre-hbf adder 2017-06-13 18:15:44 +02:00
Robert Jördens e229edd5d5 sawg: add register after hbf for timing 2017-06-12 23:08:27 +02:00
Robert Jördens 9a8a7b9102 sawg: handle clipping interpolator 
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC

This leaves a factor of two headroom for the sum of the following
effects:

  * HBF overshoot (~15 % of the step)
  * A1/A2 DDS sum

While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?

closes #743
 2017-06-12 20:33:54 +02:00
Robert Jördens 1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)" 
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
 2017-06-12 20:07:25 +02:00
Robert Jördens 332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
Robert Jördens 6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2) 
This addresses part of #743
 2017-06-12 18:59:45 +02:00
Robert Jördens 4901cb9a8a sawg: fix clr width 2017-05-22 17:46:55 +02:00
Robert Jördens 253ee950f6 sawg: fix config channel addr 2017-05-22 17:45:14 +02:00
Robert Jördens f5f662200b fir: streamline, optimize DSP extraction, left-align inputs 2016-12-20 21:39:51 +01:00
Robert Jördens cfb66117af fir: size hint for pre-adder 2016-12-20 17:58:06 +01:00
Robert Jördens f310274e39 fir: cleanup halfgen4 2016-12-20 17:58:06 +01:00
Robert Jördens 115ea67860 fir: automatically use transposed topology 2016-12-14 19:16:07 +01:00
Robert Jördens a451b675c9 Revert "fir: different adder layout" 
This reverts commit 6f50e77b409c293c1905f28e69d79403a0803866.
 2016-12-14 19:16:07 +01:00
Robert Jördens 93076b8efa fir: different adder layout 2016-12-14 19:16:07 +01:00
Robert Jördens 61abd994e9 Revert "fir: force dsp48" 
This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
 2016-12-14 19:16:07 +01:00
Robert Jördens 641d109786 fir: force dsp48 2016-12-14 19:16:07 +01:00
Robert Jördens 8381db279f sawg: wire up all HBF outputs, latency compensation in phys, simplify 2016-12-14 19:16:07 +01:00
Robert Jördens 4c27029be0 sawg: fix limit regs 2016-12-14 19:16:07 +01:00
Robert Jördens f6071a5812 sawg/hbf: tweak pipeline for timing 2016-12-08 17:00:53 +01:00
Robert Jördens b7a308d33d fir: register multiplier output 2016-12-08 17:00:39 +01:00
Robert Jördens 18e3f58c22 sawg: reduce coefficient width 2016-12-08 16:14:32 +01:00
Robert Jördens 598da09a93 sawg: fix latency 2016-12-08 15:53:35 +01:00
Robert Jördens 3eef6229cc sawg: use ParallelHBFCascade to AA [WIP] 2016-12-08 15:32:57 +01:00
Robert Jördens a629eb1665 fir: add ParallelHBFCascade 2016-12-08 15:30:26 +01:00
Robert Jördens d303225249 fir: add ParallelFIR and test 2016-12-08 15:21:04 +01:00
Robert Jördens 7e0f3edca5 gateware/dsp: add FIR and test 2016-12-07 19:14:23 +01:00