M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity
1,052 Commits 13 Branches 35 Tags 26 MiB
Commit Graph

67 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq a36c51eb83 DDS over RTIO (batch mode not supported yet) 2015-05-08 14:44:39 +08:00
Sebastien Bourdeauducq a91bb48ced gateware: adapt to misoc changes 2015-05-06 18:02:15 +08:00
Sebastien Bourdeauducq a61d701d47 rtio: decouple PHY reset from logic reset 2015-05-02 11:47:11 +08:00
Sebastien Bourdeauducq 62669f9ff2 soc: factor timer, kernel CPU and mailbox 2015-05-01 18:51:24 +08:00
Sebastien Bourdeauducq 967145f2dc watchdog support on core device (broken by bug similar to issue #19) 2015-04-29 12:58:37 +08:00
Sebastien Bourdeauducq 86c012924e targets: rename AMP->Top, merge peripherals 2015-04-28 00:18:54 +08:00
Sebastien Bourdeauducq 938e1c2842 Remove UP support. 
The only advantage of UP is to support the Papilio Pro, but that port is also very limited in other ways and the Pipistrello provides a more reasonable platform that also supports AMP.

On the other hand, RPCs on UP are difficult to implement with the session.c protocol system (without an operating system or coroutines), along with many other minor difficulties and maintainance issues. Planned features such as watchdogs in the core device are also difficult on UP.
 2015-04-27 20:43:45 +08:00
Sebastien Bourdeauducq 546996f896 coredevice,runtime: put ref_period into the ddb 2015-04-16 15:15:38 +08:00
Sebastien Bourdeauducq 61a6506484 targets/pipistrello: add mailbox memory region 2015-04-15 20:41:28 +08:00
Florent Kermarrec fd2def4951 generate MAILBOX_BASE with SoC and use it in runtime 
to avoid possible future mismatches between SoC/runtime, constants that can be easily generated from SoC should be defined this way.
 2015-04-15 20:40:28 +08:00
Robert Jördens f988ec318e pipistrello: fix csrs, make AMP default 2015-04-14 21:10:07 -06:00
Robert Jördens 9e726d7dd1 ppro: ignore all async paths 2015-04-14 18:18:48 -06:00
Robert Jördens 70916aa0c5 pipistrello: tig _all_ async paths, add timing interference report 2015-04-14 18:18:48 -06:00
Robert Jördens 066adbdeac pipistrello: timing report 2015-04-14 18:18:16 -06:00
Robert Jördens 6217cf5392 pipistrello: basesoc, cleanup 2015-04-14 18:18:16 -06:00
Sebastien Bourdeauducq 4c10182c9f rtio: refactor, use rtlink 2015-04-14 19:44:45 +08:00
Sebastien Bourdeauducq c0f1708c20 targets/pipstrello: fix mem_map 2015-04-14 19:34:14 +08:00
Sebastien Bourdeauducq a50f2c20ff targets/ppro: fix mem_map update 2015-04-11 21:59:29 +08:00
Sebastien Bourdeauducq 601f593ac4 targets/kc705: do not depend on particular Migen generated signal names 2015-04-11 21:46:57 +08:00
Florent Kermarrec bdd02a064e targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :) 2015-04-11 21:32:46 +08:00
Florent Kermarrec 24b2bd7b6f soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds 2015-04-11 21:32:11 +08:00
Sebastien Bourdeauducq fb75bd246e targets/kc705: make AMP the default 2015-04-11 17:16:25 +08:00
Sebastien Bourdeauducq b492aad1c4 targets/kc705: enable Ethernet core 2015-04-10 13:15:32 +08:00
Sebastien Bourdeauducq 44304a33b2 soc,runtime: define RTIO FUD channel number in targets 2015-04-09 00:35:11 +08:00
Sebastien Bourdeauducq 7e591bb1c7 targets: use _Peripherals/UP/AMP class names, share QC1 IO defs 2015-04-07 00:07:53 +08:00
Robert Jördens ef375b5c9c pipistrello: add double-cpu 2015-04-04 20:52:08 -06:00
Robert Jördens afc3982555 pipistrello: refactor single-cpu 2015-04-04 20:51:47 -06:00
Robert Jördens 0ae4492077 pipistrello: use mem_decoder 2015-04-04 20:51:47 -06:00
Robert Jördens e50661dac4 pipistrello: fix dcm parameters, move leds, fix names 2015-04-04 20:51:47 -06:00
Sebastien Bourdeauducq 277e038569 targets/kc705: add LED on RTIO 2015-04-04 22:07:23 +08:00
Sebastien Bourdeauducq 5f7161a7de kc705: 16 TTLs 2015-04-03 15:57:25 +08:00
Florent Kermarrec 2995f0a705 remove use of _r prefix on CSRs 2015-04-02 18:30:44 +08:00
Sebastien Bourdeauducq 88a1707ef9 soc: use new location of gpio module 2015-04-02 17:19:00 +08:00
Sebastien Bourdeauducq 5fd7f68f48 targets/kc705: dual-CPU design 2015-04-02 16:53:57 +08:00
Yann Sionneau e9092edb98 Remove one RTIO out channel to free up some space for travis builds to succeed 2015-03-30 19:51:52 +08:00
Florent Kermarrec 494c670cd2 targets/artiq_ppro: use new sdram_controller_settings parameter 2015-03-21 23:19:16 +01:00
Robert Jördens fdca0a71ff add ARTIQMidiSoC based on pipistrello 2015-03-19 11:37:15 -06:00
Sebastien Bourdeauducq 3122623c6f rtio: make 63-bit timestamp counter the default [soc] 2015-03-12 13:13:35 +01:00
Sebastien Bourdeauducq 28bce9ee40 artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
Sebastien Bourdeauducq 4e5320be28 Merge branch 'master' of https://github.com/m-labs/artiq 2015-02-28 07:34:38 -07:00
Florent Kermarrec 9cf8db2f14 adapt code to MiSoC's changes 2015-02-28 07:34:11 -07:00
Sébastien Bourdeauducq 7028d85255 targets/ppro: disable L2 2015-02-27 18:02:21 -07:00
Joe Britton 0127de9bb5 soc: add_cpu_csr_region -> add_csr_region 2015-02-27 15:02:28 -07:00
Sebastien Bourdeauducq da917f768e initial kc705 support 2015-02-26 21:50:52 -07:00
Sebastien Bourdeauducq c591f1a74d targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG 2014-12-01 18:53:29 +08:00
Sebastien Bourdeauducq 99d530e498 targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA 2014-12-01 17:31:35 +08:00
Sebastien Bourdeauducq 7166ca82d1 targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%) 2014-11-30 22:31:55 +08:00
Sebastien Bourdeauducq 1f6441948d more TTL channels and larger input FIFOs on Papilio Pro 2014-11-30 15:50:57 +08:00
Sebastien Bourdeauducq 39c4b5416f targets/ARTIQMiniSoC: 125MHz RTIO clocking 2014-11-30 01:00:27 +08:00
Sebastien Bourdeauducq 901073acf3 asynchronous RTIO 2014-11-30 00:13:54 +08:00