mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-24 19:04:02 +08:00
Remove UP support.
The only advantage of UP is to support the Papilio Pro, but that port is also very limited in other ways and the Pipistrello provides a more reasonable platform that also supports AMP. On the other hand, RPCs on UP are difficult to implement with the session.c protocol system (without an operating system or coroutines), along with many other minor difficulties and maintainance issues. Planned features such as watchdogs in the core device are also difficult on UP.
This commit is contained in:
parent
1ca49787b4
commit
938e1c2842
@ -1,9 +1,11 @@
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#!/bin/bash
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set -e
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ARTIQ_PREFIX=$(python3 -c "import artiq; print(artiq.__path__[0])")
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# Default is ppro
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BOARD=ppro
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# Default is kc705
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BOARD=kc705
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while getopts "bBrht:d:" opt
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do
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@ -21,15 +23,12 @@ do
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if [ "$OPTARG" == "kc705" ]
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then
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BOARD=kc705
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elif [ "$OPTARG" == "ppro" ]
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then
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BOARD=ppro
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elif [ "$OPTARG" == "pipistrello" ]
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then
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BOARD=pipistrello
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else
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echo "Supported targets (-t option) are:"
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echo "kc705, ppro, or pipistrello"
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echo "kc705 or pipistrello"
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exit 1
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fi
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;;
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@ -47,12 +46,12 @@ do
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echo ""
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echo "To flash everything, do not use any of the -b|-B|-r option."
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echo ""
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echo "usage: $0 [-b] [-B] [-r] [-h] [-t kc705|ppro|pipistrello] [-d path]"
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echo "usage: $0 [-b] [-B] [-r] [-h] [-t kc705|pipistrello] [-d path]"
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echo "-b Flash bitstream"
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echo "-B Flash BIOS"
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echo "-r Flash ARTIQ runtime"
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echo "-h Show this help message"
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echo "-t Target (kc705, pipistrello, ppro, default is: ppro)"
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echo "-t Target (kc705, pipistrello, default is: kc705)"
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echo "-d Directory containing the binaries to be flashed"
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exit 1
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;;
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@ -88,27 +87,7 @@ then
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BIN_PREFIX=$BIN_PATH
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fi
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if [ "$BOARD" == "ppro" ]
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then
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UDEV_RULES=99-ppro.rules
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BITSTREAM=artiq_ppro-up-papilio_pro.bin
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CABLE=papilio
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PROXY=bscan_spi_lx9_papilio.bit
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BIOS_ADDR=0x60000
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RUNTIME_ADDR=0x70000
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if [ -z "$BIN_PREFIX" ]; then BIN_PREFIX=$ARTIQ_PREFIX/binaries/ppro; fi
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search_for_proxy $PROXY
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elif [ "$BOARD" == "pipistrello" ]
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then
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UDEV_RULES=99-ppro.rules
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BITSTREAM=artiq_pipistrello-amp-pipistrello.bin
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CABLE=papilio
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PROXY=bscan_spi_lx9_csg324.bit
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BIOS_ADDR=0x170000
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RUNTIME_ADDR=0x180000
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if [ -z "$BIN_PREFIX" ]; then BIN_PREFIX=$ARTIQ_PREFIX/binaries/pipistrello; fi
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search_for_proxy $PROXY
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elif [ "$BOARD" == "kc705" ]
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if [ "$BOARD" == "kc705" ]
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then
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UDEV_RULES=99-kc705.rules
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BITSTREAM=artiq_kc705-artiqsocbasic-kc705.bit
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@ -118,6 +97,16 @@ then
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RUNTIME_ADDR=0xb00000
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if [ -z "$BIN_PREFIX" ]; then BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705; fi
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search_for_proxy $PROXY
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elif [ "$BOARD" == "pipistrello" ]
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then
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UDEV_RULES=99-papilio.rules
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BITSTREAM=artiq_pipistrello-amp-pipistrello.bin
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CABLE=papilio
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PROXY=bscan_spi_lx9_csg324.bit
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BIOS_ADDR=0x170000
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RUNTIME_ADDR=0x180000
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if [ -z "$BIN_PREFIX" ]; then BIN_PREFIX=$ARTIQ_PREFIX/binaries/pipistrello; fi
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search_for_proxy $PROXY
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fi
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# Check if neither of -b|-B|-r have been used
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@ -6,12 +6,12 @@ KC705
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The main target board for the ARTIQ core device is the KC705 development board from Xilinx.
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Papilio Pro
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Pipistrello
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-----------
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The low-cost Papilio Pro FPGA board can be used with some limitations.
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The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alternative.
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When plugged to an adapter, the NIST QC1 hardware can be used with a limited number of TTL channels. The TTL lines are mapped to RTIO channels as follows:
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When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows:
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+--------------+----------+-----------------+
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| RTIO channel | TTL line | Capability |
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@ -20,19 +20,13 @@ When plugged to an adapter, the NIST QC1 hardware can be used with a limited num
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+--------------+----------+-----------------+
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| 1 | PMT1 | Input only |
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+--------------+----------+-----------------+
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| 2 | TTL0 | Output only |
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| 2-18 | TTL0-16 | Output only |
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+--------------+----------+-----------------+
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| 3 | TTL1 | Output only |
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| 19-21 | LEDs | Output only |
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+--------------+----------+-----------------+
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| 4 | TTL2 | Output only |
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+--------------+----------+-----------------+
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| 5 | TTL3 | Output only |
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+--------------+----------+-----------------+
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| 6 | TTL4 | Output only |
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+--------------+----------+-----------------+
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| 7 | FUD | DDS driver only |
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| 22 | TTL2 | Output only |
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+--------------+----------+-----------------+
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The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Papilio Pro board), the corresponding pins on the Papilio Pro can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
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The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
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The board can accept an external RTIO clock connected to XTRIG.
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The board can accept an external RTIO clock connected to PMT2.
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@ -100,7 +100,7 @@ Create a new file ``rtio.py`` containing the following: ::
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delay(2*us)
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Connect an oscilloscope or logic analyzer to TTL0 (pin C11 on the Papilio Pro) and run ``artiq_run.py led.py``. Notice that the generated signal's period is precisely 4 microseconds, and that it has a duty cycle of precisely 50%. This is not what you would expect if the delay and the pulse were implemented with CPU-controlled GPIO: overhead from the loop management, function calls, etc. would increase the signal's period, and asymmetry in the overhead would cause duty cycle distortion.
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Connect an oscilloscope or logic analyzer to TTL0 (pin C11 on the Pipistrello) and run ``artiq_run.py led.py``. Notice that the generated signal's period is precisely 4 microseconds, and that it has a duty cycle of precisely 50%. This is not what you would expect if the delay and the pulse were implemented with CPU-controlled GPIO: overhead from the loop management, function calls, etc. would increase the signal's period, and asymmetry in the overhead would cause duty cycle distortion.
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Instead, inside the core device, output timing is generated by the gateware and the CPU only programs switching commands with certain timestamps that the CPU computes. This guarantees precise timing as long as the CPU can keep generating timestamps that are increasing fast enough. In case it fails to do that (and attempts to program an event with a timestamp in the past), the :class:`artiq.coredevice.runtime_exceptions.RTIOUnderflow` exception is raised. The kernel causing it may catch it (using a regular ``try... except...`` construct), or it will be propagated to the host.
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@ -138,7 +138,7 @@ Try the following code and observe the generated pulses on a 2-channel oscillosc
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self.ttl1.pulse(4*us)
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delay(4*us)
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TTL1 is assigned to the pin C10 of the Papilio Pro. The name of the attributes (``ttl0`` and ``ttl1``) is used to look up hardware in the device database.
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TTL1 is assigned to the pin C10 of the Pipistrello. The name of the attributes (``ttl0`` and ``ttl1``) is used to look up hardware in the device database.
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Within a parallel block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
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@ -8,9 +8,9 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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* Install the FPGA vendor tools (e.g. Xilinx ISE and/or Vivado):
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* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Papilio Pro) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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* The Papilio Pro is supported by Webpack, the KC705 is not.
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* The Pipistrello is supported by Webpack, the KC705 is not.
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* During the Xilinx toolchain installation, uncheck ``Install cable drivers`` (they are not required as we use better and open source alternatives).
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@ -52,7 +52,7 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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$ make -j4
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$ sudo make install
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* Install JTAG tools needed to program Papilio Pro and KC705:
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* Install JTAG tools needed to program the Pipistrello and KC705:
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::
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@ -69,14 +69,14 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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The purpose of the flash proxy bitstream is to give programming software fast JTAG access to the flash connected to the FPGA.
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* Papilio Pro:
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* Pipistrello:
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::
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$ cd ~/artiq-dev
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$ git clone https://github.com/GadgetFactory/Papilio-Loader
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$ wget http://www.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit
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Then copy ``~/artiq-dev/Papilio-Loader/xc3sprog/trunk/bscan_spi/bscan_spi_lx9_papilio.bit`` to ``~/.migen``, ``/usr/local/share/migen`` or ``/usr/share/migen``.
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Then copy ``~/artiq-dev/bscan_spi_lx45_csg324.bit`` to ``~/.migen``, ``/usr/local/share/migen`` or ``/usr/share/migen``.
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* KC705:
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@ -107,9 +107,9 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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* Then, build and flash the ARTIQ runtime: ::
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$ cd ~/artiq-dev/artiq/soc/runtime && make runtime.fbi
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$ ~/artiq-dev/artiq/artiq/frontend/artiq_flash.sh -t ppro -d $PWD -r
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$ ~/artiq-dev/artiq/artiq/frontend/artiq_flash.sh -t pipistrello -d $PWD -r
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.. note:: The `-t` option specifies the board your are targeting. Available options are `ppro` for Papilio Pro, `kc705` for KC705 and `pipistrello` for Pipistrello.
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.. note:: The `-t` option specifies the board your are targeting. Available options are ``kc705`` and ``pipistrello``.
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* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the bitstream that was newly written into the flash): ::
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@ -192,7 +192,7 @@ This command installs all the required packages: ::
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Note that ARTIQ requires Python 3.4 or above.
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To set user permissions on the JTAG and serial ports of the Papilio Pro, create a ``/etc/udev/rules.d/30-usb-papilio-pro.rules`` file containing the following: ::
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To set user permissions on the JTAG and serial ports of the Pipistrello, create a ``/etc/udev/rules.d/30-usb-papilio.rules`` file containing the following: ::
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SUBSYSTEM=="usb", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", GROUP="dialout"
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@ -1,24 +1,7 @@
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include $(MSCDIR)/software/common.mak
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OBJECTS := isr.o flash_storage.o elf_loader.o services.o session.o log.o test_mode.o kloader.o main.o
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OBJECTS_KSUPPORT := exception_jmp.o exceptions.o rtio.o dds.o
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# NOTE: this does not handle dependencies well. Run "make clean"
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# when switching between UP and AMP.
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UNIPROCESSOR := $(shell printf "\#include <generated/csr.h>\nCSR_KERNEL_CPU_BASE" | $(CC_normal) $(CFLAGS) -E - | tail -n 1 | grep -c CSR_KERNEL_CPU_BASE)
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ifeq ($(UNIPROCESSOR),0)
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OBJECTS += mailbox.o ksupport_data.o
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OBJECTS_KSUPPORT += mailbox.o bridge.o ksupport.o
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CFLAGS += -DARTIQ_AMP
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SERVICE_TABLE_INPUT = ksupport.elf
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else
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ifeq ($(UNIPROCESSOR),1)
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OBJECTS += $(OBJECTS_KSUPPORT)
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else
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$(error failed to determine UP/AMP build)
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endif
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endif
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OBJECTS := isr.o flash_storage.o elf_loader.o services.o session.o log.o test_mode.o kloader.o mailbox.o ksupport_data.o main.o
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OBJECTS_KSUPPORT := ksupport.o exception_jmp.o exceptions.o mailbox.o bridge.o rtio.o dds.o
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CFLAGS += -Ilwip/src/include -Iliblwip
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@ -57,8 +40,8 @@ ksupport.elf: $(OBJECTS_KSUPPORT)
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ksupport_data.o: ksupport.bin
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$(LD) -r -b binary -o $@ $<
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service_table.h: $(SERVICE_TABLE_INPUT) gen_service_table.py
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@echo " GEN " $@ && ./gen_service_table.py $(SERVICE_TABLE_INPUT) > $@
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service_table.h: ksupport.elf gen_service_table.py
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@echo " GEN " $@ && ./gen_service_table.py ksupport.elf > $@
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services.c: service_table.h
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@ -2,6 +2,8 @@
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import sys
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from elftools.elf.elffile import ELFFile
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services = [
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("syscalls", [
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@ -24,17 +26,7 @@ services = [
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]
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def print_up():
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for name, contents in services:
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print("static const struct symbol {}[] = {{".format(name))
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for name, value in contents:
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print(" {{\"{}\", {}}},".format(name, value))
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print(" {NULL, NULL}")
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print("};")
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def print_amp(ksupport_elf_filename):
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from elftools.elf.elffile import ELFFile
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def print_service_table(ksupport_elf_filename):
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with open(ksupport_elf_filename, "rb") as f:
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elf = ELFFile(f)
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symtab = elf.get_section_by_name(b".symtab")
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@ -50,10 +42,8 @@ def print_amp(ksupport_elf_filename):
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def main():
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if len(sys.argv) == 1:
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print_up()
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elif len(sys.argv) == 2:
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print_amp(sys.argv[1])
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if len(sys.argv) == 2:
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print_service_table(sys.argv[1])
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else:
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print("Incorrect number of command line arguments")
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sys.exit(1)
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@ -49,12 +49,10 @@ static int symtab_add(const char *name, void *target)
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int kloader_load(void *buffer, int length)
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{
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#ifdef ARTIQ_AMP
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if(!kernel_cpu_reset_read()) {
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log("BUG: attempted to load while kernel CPU running");
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return 0;
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}
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#endif
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symtab_init();
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return load_elf(
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resolve_service_symbol, symtab_add,
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@ -66,8 +64,6 @@ kernel_function kloader_find(const char *name)
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return find_symbol(symtab, name);
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}
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#ifdef ARTIQ_AMP
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extern char _binary_ksupport_bin_start;
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extern char _binary_ksupport_bin_end;
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@ -107,5 +103,3 @@ void kloader_stop_kernel(void)
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{
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kernel_cpu_reset_write(1);
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}
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#endif
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@ -9,11 +9,9 @@ typedef void (*kernel_function)(void);
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int kloader_load(void *buffer, int length);
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kernel_function kloader_find(const char *name);
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#ifdef ARTIQ_AMP
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void kloader_start_bridge(void);
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void kloader_start_idle_kernel(void);
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void kloader_start_user_kernel(kernel_function k);
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void kloader_stop_kernel(void);
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#endif
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#endif /* __KLOADER_H */
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@ -3,15 +3,8 @@
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#include <generated/csr.h>
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#ifdef ARTIQ_AMP
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#include "mailbox.h"
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#include "messages.h"
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#else
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#include <system.h>
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#include "exceptions.h"
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#include "rtio.h"
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#include "dds.h"
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#endif
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#include "log.h"
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#include "kloader.h"
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@ -73,18 +66,14 @@ void session_start(void)
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buffer_out_index_data = 0;
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buffer_out_index_mem = 0;
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memset(&buffer_out[4], 0, 4);
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#ifdef ARTIQ_AMP
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kloader_stop_kernel();
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#endif
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user_kernel_state = USER_KERNEL_NONE;
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}
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void session_end(void)
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{
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#ifdef ARTIQ_AMP
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kloader_stop_kernel();
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kloader_start_idle_kernel();
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#endif
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}
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/* host to device */
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@ -204,53 +193,6 @@ static int send_rpc_request(int rpc_num, va_list args)
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return 1;
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}
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#ifndef ARTIQ_AMP
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static int rpc_reply_eid;
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static int rpc_reply_retval;
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int rpc(int rpc_num, ...)
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{
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va_list args;
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va_start(args, rpc_num);
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send_rpc_request(rpc_num, args);
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va_end(args);
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user_kernel_state = USER_KERNEL_WAIT_RPC;
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/*while(user_kernel_state == USER_KERNEL_WAIT_RPC)
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comm_service();*/
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if(rpc_reply_eid != EID_NONE)
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exception_raise(rpc_reply_eid);
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return rpc_reply_retval;
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}
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/* assumes output buffer is empty when called */
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static void run_kernel_up(kernel_function k)
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{
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void *jb;
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int eid;
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long long eparams[3];
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jb = exception_push();
|
||||
if(exception_setjmp(jb)) {
|
||||
eid = exception_getid(eparams);
|
||||
buffer_out[8] = REMOTEMSG_TYPE_KERNEL_EXCEPTION;
|
||||
memcpy(&buffer_out[9], &eid, 4);
|
||||
memcpy(&buffer_out[13], eparams, 3*8);
|
||||
submit_output(9+4+3*8);
|
||||
} else {
|
||||
dds_init();
|
||||
rtio_init();
|
||||
flush_cpu_icache();
|
||||
k();
|
||||
exception_pop(1);
|
||||
buffer_out[8] = REMOTEMSG_TYPE_KERNEL_FINISHED;
|
||||
submit_output(9);
|
||||
}
|
||||
}
|
||||
#endif /* !ARTIQ_AMP */
|
||||
|
||||
static int process_input(void)
|
||||
{
|
||||
switch(buffer_in[8]) {
|
||||
@ -321,35 +263,22 @@ static int process_input(void)
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef ARTIQ_AMP
|
||||
kloader_start_user_kernel(k);
|
||||
user_kernel_state = USER_KERNEL_RUNNING;
|
||||
#else
|
||||
user_kernel_state = USER_KERNEL_RUNNING;
|
||||
run_kernel_up(k);
|
||||
user_kernel_state = USER_KERNEL_LOADED;
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
case REMOTEMSG_TYPE_RPC_REPLY: {
|
||||
#ifdef ARTIQ_AMP
|
||||
struct msg_rpc_reply reply;
|
||||
#endif
|
||||
|
||||
if(user_kernel_state != USER_KERNEL_WAIT_RPC) {
|
||||
log("Unsolicited RPC reply");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef ARTIQ_AMP
|
||||
reply.type = MESSAGE_TYPE_RPC_REPLY;
|
||||
memcpy(&reply.eid, &buffer_in[9], 4);
|
||||
memcpy(&reply.retval, &buffer_in[13], 4);
|
||||
mailbox_send_and_wait(&reply);
|
||||
#else
|
||||
memcpy(&rpc_reply_eid, &buffer_in[9], 4);
|
||||
memcpy(&rpc_reply_retval, &buffer_in[13], 4);
|
||||
#endif
|
||||
user_kernel_state = USER_KERNEL_RUNNING;
|
||||
break;
|
||||
}
|
||||
@ -411,7 +340,6 @@ int session_input(void *data, int len)
|
||||
return consumed;
|
||||
}
|
||||
|
||||
#ifdef ARTIQ_AMP
|
||||
/* assumes output buffer is empty when called */
|
||||
static void process_kmsg(struct msg_base *umsg)
|
||||
{
|
||||
@ -470,7 +398,6 @@ static void process_kmsg(struct msg_base *umsg)
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* ARTIQ_AMP */
|
||||
|
||||
void session_poll(void **data, int *len)
|
||||
{
|
||||
@ -478,7 +405,6 @@ void session_poll(void **data, int *len)
|
||||
|
||||
l = get_out_packet_len();
|
||||
|
||||
#ifdef ARTIQ_AMP
|
||||
/* If the output buffer is available,
|
||||
* check if the kernel CPU has something to transmit.
|
||||
*/
|
||||
@ -492,7 +418,6 @@ void session_poll(void **data, int *len)
|
||||
}
|
||||
l = get_out_packet_len();
|
||||
}
|
||||
#endif
|
||||
|
||||
*len = l - buffer_out_index_data;
|
||||
*data = &buffer_out[buffer_out_index_data];
|
||||
|
||||
@ -7,14 +7,13 @@
|
||||
#include <generated/csr.h>
|
||||
#include <console.h>
|
||||
|
||||
#include "dds.h"
|
||||
#include "test_mode.h"
|
||||
|
||||
#ifdef ARTIQ_AMP
|
||||
|
||||
#include "kloader.h"
|
||||
#include "mailbox.h"
|
||||
#include "messages.h"
|
||||
#include "dds.h"
|
||||
#include "test_mode.h"
|
||||
|
||||
/* bridge access functions */
|
||||
|
||||
static void amp_bridge_init(void)
|
||||
{
|
||||
@ -102,48 +101,7 @@ static void p_ddsfud(void)
|
||||
mailbox_send_and_wait(&msg);
|
||||
}
|
||||
|
||||
#else /* ARTIQ_AMP */
|
||||
|
||||
#include "rtio.h"
|
||||
|
||||
static void p_ttlout(int n, int value)
|
||||
{
|
||||
rtio_init();
|
||||
rtio_set_oe(rtio_get_counter() + 8000, n, 1);
|
||||
rtio_set_o(rtio_get_counter() + 8000, n, value);
|
||||
}
|
||||
|
||||
static void p_ddssel(int channel)
|
||||
{
|
||||
DDS_WRITE(DDS_GPIO, channel);
|
||||
}
|
||||
|
||||
static void p_ddsreset(void)
|
||||
{
|
||||
unsigned int g;
|
||||
|
||||
g = DDS_READ(DDS_GPIO);
|
||||
DDS_WRITE(DDS_GPIO, g | (1 << 7));
|
||||
DDS_WRITE(DDS_GPIO, g);
|
||||
}
|
||||
|
||||
static unsigned int p_ddsread(unsigned int address)
|
||||
{
|
||||
return DDS_READ(address);
|
||||
}
|
||||
|
||||
static void p_ddswrite(unsigned int address, unsigned int data)
|
||||
{
|
||||
DDS_WRITE(address, data);
|
||||
}
|
||||
|
||||
static void p_ddsfud(void)
|
||||
{
|
||||
rtio_init();
|
||||
rtio_fud(rtio_get_counter() + 8000);
|
||||
}
|
||||
|
||||
#endif /* ARTIQ_AMP */
|
||||
/* */
|
||||
|
||||
static void leds(char *value)
|
||||
{
|
||||
@ -462,9 +420,7 @@ void test_main(void)
|
||||
{
|
||||
char buffer[64];
|
||||
|
||||
#ifdef ARTIQ_AMP
|
||||
amp_bridge_init();
|
||||
#endif
|
||||
|
||||
while(1) {
|
||||
putsnonl("\e[1mtest>\e[0m ");
|
||||
|
||||
@ -94,18 +94,6 @@ set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
|
||||
set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
|
||||
""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
|
||||
|
||||
class UP(_Peripherals):
|
||||
def __init__(self, *args, **kwargs):
|
||||
_Peripherals.__init__(self, *args, **kwargs)
|
||||
|
||||
rtio_csrs = self.rtio.get_csrs()
|
||||
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
|
||||
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
|
||||
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
|
||||
|
||||
self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
|
||||
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
|
||||
|
||||
|
||||
class AMP(_Peripherals):
|
||||
csr_map = {
|
||||
|
||||
@ -121,20 +121,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
|
||||
self.comb += dds_pads.fud_n.eq(~fud)
|
||||
|
||||
|
||||
class UP(_Peripherals):
|
||||
def __init__(self, platform, **kwargs):
|
||||
_Peripherals.__init__(self, platform, **kwargs)
|
||||
|
||||
rtio_csrs = self.rtio.get_csrs()
|
||||
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
|
||||
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
|
||||
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
|
||||
rtio_csrs)
|
||||
|
||||
self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
|
||||
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
|
||||
|
||||
|
||||
class AMP(_Peripherals):
|
||||
csr_map = {
|
||||
"kernel_cpu": 14
|
||||
|
||||
@ -1,131 +0,0 @@
|
||||
from migen.fhdl.std import *
|
||||
from migen.bank.description import *
|
||||
from migen.bank import wbgen
|
||||
from mibuild.generic_platform import *
|
||||
|
||||
from misoclib.com import gpio
|
||||
from misoclib.soc import mem_decoder
|
||||
from misoclib.mem.sdram.core.minicon import MiniconSettings
|
||||
from targets.ppro import BaseSoC
|
||||
|
||||
from artiq.gateware import rtio, ad9858, nist_qc1
|
||||
from artiq.gateware.rtio.phy import ttl_simple
|
||||
|
||||
|
||||
class _TestGen(Module):
|
||||
def __init__(self, pad):
|
||||
divc = Signal(15)
|
||||
ce = Signal()
|
||||
self.sync += Cat(divc, ce).eq(divc + 1)
|
||||
|
||||
sr = Signal(8, reset=0b10101000)
|
||||
self.sync += If(ce, sr.eq(Cat(sr[1:], sr[0])))
|
||||
self.comb += pad.eq(sr[0])
|
||||
|
||||
|
||||
class _RTIOMiniCRG(Module, AutoCSR):
|
||||
def __init__(self, platform):
|
||||
self._clock_sel = CSRStorage()
|
||||
self.clock_domains.cd_rtio = ClockDomain()
|
||||
|
||||
# 80MHz -> 125MHz
|
||||
rtio_internal_clk = Signal()
|
||||
self.specials += Instance("DCM_CLKGEN",
|
||||
p_CLKFXDV_DIVIDE=2,
|
||||
p_CLKFX_DIVIDE=16, p_CLKFX_MD_MAX=1.6, p_CLKFX_MULTIPLY=25,
|
||||
p_CLKIN_PERIOD=12.5, p_SPREAD_SPECTRUM="NONE",
|
||||
p_STARTUP_WAIT="FALSE",
|
||||
|
||||
i_CLKIN=ClockSignal(), o_CLKFX=rtio_internal_clk,
|
||||
i_FREEZEDCM=0, i_RST=ResetSignal())
|
||||
|
||||
rtio_external_clk = platform.request("xtrig")
|
||||
platform.add_period_constraint(rtio_external_clk, 8.0)
|
||||
self.specials += Instance("BUFGMUX",
|
||||
i_I0=rtio_internal_clk,
|
||||
i_I1=rtio_external_clk,
|
||||
i_S=self._clock_sel.storage,
|
||||
o_O=self.cd_rtio.clk)
|
||||
|
||||
platform.add_platform_command("""
|
||||
NET "{int_clk}" TNM_NET = "GRPint_clk";
|
||||
NET "{ext_clk}" TNM_NET = "GRPext_clk";
|
||||
NET "sys_clk" TNM_NET = "GRPsys_clk";
|
||||
TIMESPEC "TSfix_ise1" = FROM "GRPint_clk" TO "GRPsys_clk" TIG;
|
||||
TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
|
||||
TIMESPEC "TSfix_ise3" = FROM "GRPext_clk" TO "GRPsys_clk" TIG;
|
||||
TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPext_clk" TIG;
|
||||
TIMESPEC "TSfix_ise5" = FROM "GRPext_clk" TO "GRPint_clk" TIG;
|
||||
TIMESPEC "TSfix_ise6" = FROM "GRPint_clk" TO "GRPext_clk" TIG;
|
||||
""", int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
|
||||
|
||||
|
||||
class UP(BaseSoC):
|
||||
csr_map = {
|
||||
"rtio": None, # mapped on Wishbone instead
|
||||
"rtiocrg": 13
|
||||
}
|
||||
csr_map.update(BaseSoC.csr_map)
|
||||
mem_map = {
|
||||
"rtio": 0x20000000, # (shadow @0xa0000000)
|
||||
"dds": 0x50000000, # (shadow @0xd0000000)
|
||||
}
|
||||
mem_map.update(BaseSoC.mem_map)
|
||||
|
||||
def __init__(self, platform, cpu_type="or1k",
|
||||
with_test_gen=False, **kwargs):
|
||||
BaseSoC.__init__(self, platform,
|
||||
cpu_type=cpu_type,
|
||||
sdram_controller_settings=MiniconSettings(),
|
||||
**kwargs)
|
||||
platform.add_extension(nist_qc1.papilio_adapter_io)
|
||||
|
||||
self.submodules.leds = gpio.GPIOOut(Cat(
|
||||
platform.request("user_led", 0),
|
||||
platform.request("ext_led", 0)))
|
||||
|
||||
self.comb += [
|
||||
platform.request("ttl_l_tx_en").eq(1),
|
||||
platform.request("ttl_h_tx_en").eq(1)
|
||||
]
|
||||
|
||||
# RTIO channels
|
||||
rtio_channels = []
|
||||
for i in range(2):
|
||||
phy = ttl_simple.Inout(platform.request("pmt", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel(phy.rtlink))
|
||||
for i in range(5):
|
||||
phy = ttl_simple.Output(platform.request("ttl", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel(phy.rtlink))
|
||||
|
||||
fud = Signal()
|
||||
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_channels))
|
||||
phy = ttl_simple.Output(fud)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel(phy.rtlink))
|
||||
|
||||
# RTIO core
|
||||
self.submodules.rtiocrg = _RTIOMiniCRG(platform)
|
||||
self.submodules.rtio = rtio.RTIO(rtio_channels,
|
||||
clk_freq=125000000,
|
||||
counter_width=32)
|
||||
|
||||
rtio_csrs = self.rtio.get_csrs()
|
||||
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
|
||||
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
|
||||
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000,
|
||||
32, rtio_csrs)
|
||||
|
||||
if with_test_gen:
|
||||
self.submodules.test_gen = _TestGen(platform.request("ttl", 8))
|
||||
|
||||
dds_pads = platform.request("dds")
|
||||
self.submodules.dds = ad9858.AD9858(dds_pads)
|
||||
self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
|
||||
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
|
||||
self.comb += dds_pads.fud_n.eq(~fud)
|
||||
|
||||
|
||||
default_subtarget = UP
|
||||
Loading…
Reference in New Issue
Block a user