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targets: rename AMP->Top, merge peripherals
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@ -90,7 +90,7 @@ fi
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if [ "$BOARD" == "kc705" ]
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then
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UDEV_RULES=99-kc705.rules
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BITSTREAM=artiq_kc705-artiqsocbasic-kc705.bit
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BITSTREAM=artiq_kc705-top-kc705.bit
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CABLE=jtaghs1_fast
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PROXY=bscan_spi_kc705.bit
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BIOS_ADDR=0xaf0000
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@ -100,7 +100,7 @@ then
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elif [ "$BOARD" == "pipistrello" ]
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then
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UDEV_RULES=99-papilio.rules
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BITSTREAM=artiq_pipistrello-amp-pipistrello.bin
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BITSTREAM=artiq_pipistrello-top-pipistrello.bin
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CABLE=papilio
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PROXY=bscan_spi_lx9_csg324.bit
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BIOS_ADDR=0x170000
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@ -366,16 +366,14 @@ int main(void)
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irq_setie(1);
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uart_init();
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#ifdef ARTIQ_AMP
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puts("ARTIQ runtime built "__DATE__" "__TIME__" for AMP systems\n");
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#else
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puts("ARTIQ runtime built "__DATE__" "__TIME__" for UP systems\n");
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#endif
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puts("ARTIQ runtime built "__DATE__" "__TIME__"\n");
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#ifdef CSR_ETHMAC_BASE
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puts("Accepting sessions on Ethernet");
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#else
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puts("Accepting sessions on serial link");
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#endif
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puts("Press 't' to enter test mode...");
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blink_led();
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@ -30,15 +30,17 @@ class _RTIOCRG(Module, AutoCSR):
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o_O=self.cd_rtio.clk)
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class _Peripherals(MiniSoC):
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class Top(MiniSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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"rtiocrg": 13,
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"kernel_cpu": 14
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}
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csr_map.update(MiniSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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@ -94,34 +96,27 @@ set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
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set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
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""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
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class AMP(_Peripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_Peripherals.csr_map)
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mem_map = {
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(_Peripherals.mem_map)
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def __init__(self, platform, *args, **kwargs):
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_Peripherals.__init__(self, platform, *args, **kwargs)
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# Kernel CPU
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
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self.add_memory_region("mailbox", self.mem_map["mailbox"] + 0x80000000, 4)
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.mailbox.i2)
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self.add_memory_region("mailbox",
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self.mem_map["mailbox"] + 0x80000000, 4)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
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self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
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rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]),
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self.dds.bus)
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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default_subtarget = AMP
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default_subtarget = Top
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@ -51,15 +51,17 @@ TIMESPEC "TSfix_ise6" = FROM "GRPint_clk" TO "GRPext_clk" TIG;
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""", int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
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class _Peripherals(BaseSoC):
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class Top(BaseSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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"rtiocrg": 13,
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"kernel_cpu": 14
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}
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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@ -120,20 +122,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules.dds = ad9858.AD9858(dds_pads)
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self.comb += dds_pads.fud_n.eq(~fud)
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class AMP(_Peripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_Peripherals.csr_map)
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mem_map = {
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(_Peripherals.mem_map)
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def __init__(self, platform, *args, **kwargs):
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_Peripherals.__init__(self, platform, **kwargs)
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# Kernel CPU
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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self.submodules.mailbox = amp.Mailbox()
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@ -156,4 +145,4 @@ class AMP(_Peripherals):
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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default_subtarget = AMP
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default_subtarget = Top
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