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152 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 1f2182d4c7 kasli: default to hardware v2 2020-05-07 19:15:03 +08:00
Sebastien Bourdeauducq b83afedf43 kasli: light up ERROR LED on panic 2020-05-07 19:06:10 +08:00
Sebastien Bourdeauducq 7e400a78f4 kasli: compile tester for hw 2.0 by default 2020-04-28 16:07:56 +08:00
Sebastien Bourdeauducq d19f28fa84 kasli: v2 clocking WIP, remove SFP LEDs from RTIO 2020-04-23 23:02:18 +08:00
Sebastien Bourdeauducq 42af76326f kasli: enlarge integrated CPU SRAM for DRTIO masters 
Required by the bootloader netboot support.
 2019-11-01 10:15:13 +08:00
Sebastien Bourdeauducq 462cf5967e bootloader: add netboot support 2019-10-30 21:23:42 +08:00
Sebastien Bourdeauducq 314d9b5d06 kasli: default to 125MHz frequency for DRTIO 
This is the consistent and most common option. Sayma will also eventually move to it.
 2019-10-08 12:59:52 +08:00
Sebastien Bourdeauducq 21021beb08 kasli: remove opticlock (moved to kasli_generic) 2019-09-09 15:03:10 +08:00
Robert Jördens ead9a42842 kasli: remove VLBAIMaster, VLBAISatellite variants 2019-05-08 15:58:25 +00:00
Robert Jördens 0c9b810501 kasli: remove PTB/PTB2/LUH/HUB variants 
see sinara-systems and nix-scripts repos
 2019-05-08 15:51:18 +00:00
David Nadlinger 4d215cf541 firmware: Add Si5324 config for 125 MHz ext ref 
PLL divider settings as suggested by DSPLLsim 5.1.
 2019-04-15 22:22:19 +01:00
Chris Ballance 4499ef1748 kasli: only add moninj core if there are probes to monitor 2019-03-24 14:09:52 +08:00
Sebastien Bourdeauducq de3992bbdd kasli: remove HUST variants (supported by kasli_generic) 2019-02-23 15:44:17 +08:00
Sebastien Bourdeauducq 1c35c051a5 kasli: remove variants supported by generic builder 2019-02-22 23:08:49 +08:00
Sebastien Bourdeauducq ff4e4f15ed kasli: expose base SoC classes 2019-02-12 18:33:27 +08:00
Sebastien Bourdeauducq 1cfd26dc2e kasli: add UNSW variant 2019-02-08 17:51:51 +08:00
Sebastien Bourdeauducq b56c7cec1e kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target 
Urukul sync is not reliable at 125/1000
 2019-02-05 11:24:45 +08:00
Sebastien Bourdeauducq 07b5b0d36d kasli: adapt Master target to new hardware 2019-01-24 18:27:15 +08:00
Sebastien Bourdeauducq 154269b77a kasli: fix HUST satellite Urukul 2019-01-23 17:59:43 +08:00
Sebastien Bourdeauducq d7e6f104d2 kasli: add HUST variants 2019-01-23 14:11:51 +08:00
Sebastien Bourdeauducq 81f2b2c864 kasli: remove unpopulated Tester EEMs 
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
 2019-01-23 12:14:44 +08:00
Sebastien Bourdeauducq 9ee5fea88d kasli: support optional SATA port for DRTIO 2019-01-22 18:06:48 +08:00
Sebastien Bourdeauducq bff8c8cb05 kasli: add Berkeley variant 2019-01-21 17:44:17 +08:00
David Nadlinger 1c71ae636a examples: Add edge counters to kasli_tester variant 
This enables test_edge_counter on the CI system.
 2019-01-15 10:55:07 +00:00
Sebastien Bourdeauducq 77126ce5b3 kasli: use hwrev 1.1 by default for DRTIO examples 2019-01-02 23:04:20 +08:00
Sebastien Bourdeauducq ab9ca0ee0a kasli: use 150MHz for DRTIO by default (Sayma compatibility) 2019-01-02 23:03:57 +08:00
Sebastien Bourdeauducq cc58318500 siphaser: autocalibrate skew using RX synchronizer 
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
 2019-01-02 22:29:27 +08:00
Sebastien Bourdeauducq 53e79f553f Merge branch 'master' into new 2018-11-19 11:54:50 +08:00
Sebastien Bourdeauducq 78d4b3a7da gateware/targets: expose variant lists 
This allows writing scripts that build all variants.
 2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq c990b5e4f1 Merge remote-tracking branch 'origin/master' into new 2018-11-08 20:21:56 +08:00
Sebastien Bourdeauducq ad0254c17b Merge branch 'switching125' into new 2018-11-07 22:03:18 +08:00
Sebastien Bourdeauducq efd735a6ab Revert "drtio: monitor RTIOClockMultiplier PLL (#1155)" 
This reverts commit 469a66db61.
 2018-11-07 22:01:03 +08:00
Robert Jördens ba4bf6e59b kasli: don't pass rtio pll feedback through bufg 
UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 11:58:55 +00:00
Robert Jördens b6e4961b0f kasli: lower RTIO clock jitter 
* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 11:43:19 +00:00
Robert Jördens e17e458c58 ptb2: add sync to urukul0 for ad9910 usage 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 10:06:51 +00:00
Robert Jördens 31f68ddf6c Merge branch 'urukul-sync' 
* urukul-sync: (29 commits)
  urukul: flake8 [nfc]
  ad9910: flake8 [nfc]
  urukul/ad9910 test: remove unused import
  test_urukul: relax speed
  urukul,ad9910: print speed metrics
  kasli: add PTB2 (external clock and SYNC)
  kasli: add sync to LUH, HUB, Opticlock
  kasli_tester: urukul0 mmcx clock defunct
  test_ad9910: relax ifc mode read
  tests: add Urukul-AD9910 HITL unittests including SYNC
  ad9910: add init bit explanation
  test: add Urukul CPLD HITL tests
  ad9910: fiducial timestamp for tracking phase mode
  ad9910: add phase modes
  ad9910: fix pll timeout loop
  tester: add urukul sync
  ptb: back out urukul-sync
  ad9910: add IO_UPDATE alignment and tuning
  urukul: set up sync_in generator
  ad9910: add io_update alignment measurement
  ...

close #1143
 2018-11-05 19:54:30 +01:00
Robert Jördens 32d538f72b kasli: add PTB2 (external clock and SYNC) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:16 +01:00
Robert Jördens d8a5951a13 kasli: add sync to LUH, HUB, Opticlock 
for #1143, also add missing LUH device db

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:14 +01:00
Robert Jördens 4269d5ad5c tester: add urukul sync 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:52 +01:00
Robert Jördens 60d3bc63a7 ptb: back out urukul-sync 
... for backwards compatibility.

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:50 +01:00
Robert Jördens 0433e8f4fe urukul: add sync_in generator 
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:30 +01:00
Sebastien Bourdeauducq bc4a8157c0 kasli: add tsinghua2 2018-11-01 18:26:37 +08:00
Sebastien Bourdeauducq 6357a50d33 kasli: update nudt variant 2018-10-15 18:04:57 +08:00
Sebastien Bourdeauducq 469a66db61 drtio: monitor RTIOClockMultiplier PLL (#1155) 
Debugging by Tom Harty
 2018-10-08 14:50:02 +02:00
Sebastien Bourdeauducq 86fe6b0594 kasli: add NUDT variant 2018-10-04 23:20:09 +08:00
Sebastien Bourdeauducq a89bd6b684 kasli: swap Urukul EEMs for Tester 
Updated to Urukul 1.3.
 2018-10-04 23:19:31 +08:00
Sebastien Bourdeauducq 9f96b6bcda kasli: use 125MHz DRTIO freq for testing 2018-10-04 10:41:01 +08:00
Sebastien Bourdeauducq 969a305c5a Merge branch 'master' into switching125 2018-10-04 10:08:42 +08:00
Robert Jördens d0ee2c2955 opticlock: external 100 MHz 2018-09-28 19:05:18 +02:00
Sebastien Bourdeauducq 3b3fddb5a4 kasli: add mitll2 2018-09-27 23:21:52 +08:00