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ad4f00e93d
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simplesoc_ecp5: load firmware
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2019-06-06 18:11:54 +08:00 |
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a53c470d17
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nmigen: bump
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2019-06-06 18:11:31 +08:00 |
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713f644072
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minerva: bump
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2019-06-06 18:04:56 +08:00 |
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a203307108
|
reorganize
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2019-06-06 17:25:11 +08:00 |
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63664ab959
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build .bin firmware image
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2019-06-06 17:17:45 +08:00 |
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d2391e0aa1
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build firmware with Nix
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2019-06-06 13:19:17 +08:00 |
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b6c53406ea
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show LLVM in hydra
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2019-06-06 12:24:48 +08:00 |
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3edb51a646
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fix syntax issue
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2019-06-06 12:12:40 +08:00 |
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85f7b2bf15
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use overlay instead of passing llvm/rustc/cargo around
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2019-06-06 12:05:48 +08:00 |
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78f67f82d3
|
firmware: simulable demo
Run:
qemu-system-riscv32 -nographic -machine sifive_u -kernel target/riscv32imc-unknown-none-elf/release/helloworld
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2019-06-06 10:33:29 +08:00 |
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b5ac2e7303
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add simple Rust firmware (WIP)
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2019-06-06 00:12:17 +08:00 |
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f707295646
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use the GNU linker
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2019-06-06 00:07:53 +08:00 |
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cf86c11dce
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binutils: use unknown-elf
|
2019-06-06 00:06:29 +08:00 |
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aa1c3726f3
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attempt to use lld linker
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2019-06-05 23:46:29 +08:00 |
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d5c288c20b
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rustc: disable lld
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2019-06-05 23:42:39 +08:00 |
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1361c6ae9e
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Revert "llvm: only build x86 and riscv"
This reverts commit b17ec6fb1f.
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2019-06-05 23:41:22 +08:00 |
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b17ec6fb1f
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llvm: only build x86 and riscv
Attempting to fix llvm-lld breakage on msp430 by disabling msp430.
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2019-06-05 23:19:51 +08:00 |
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52cc7722a0
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add nix-shell file for firmware compilation
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2019-06-05 23:08:55 +08:00 |
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6ad1d993c6
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rustc: remove riscv32i support
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2019-06-05 23:07:49 +08:00 |
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f929be260a
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build cargo
|
2019-06-05 23:06:57 +08:00 |
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2c3fc22963
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Use riscv32imc for Rust core crate
Some other crates have issues with riscv32i.
|
2019-06-05 23:06:03 +08:00 |
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|
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14c7b4890c
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rustc: enable lld
|
2019-06-05 23:05:15 +08:00 |
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d02da47167
|
minerva: bump
|
2019-05-25 12:23:17 +08:00 |
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2f3c1824a6
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nmigen: bump
|
2019-05-15 18:55:32 +08:00 |
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ec09c09cf3
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rust-riscv32i-crates: use external compiler_builtins
|
2019-05-14 20:35:40 +08:00 |
|
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a0690fe0e2
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rust-riscv32i-crates: disable compiler_builtins
|
2019-05-14 19:58:13 +08:00 |
|
|
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9e93a9cf39
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rustc: make llvm override compatible with nixos-unstable
|
2019-05-14 19:17:16 +08:00 |
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9f4538555e
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fix previous commit
|
2019-05-14 19:16:52 +08:00 |
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e9b005d50a
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mark riscv rustc
|
2019-05-14 19:05:30 +08:00 |
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677ddefff2
|
mark riscv llvm
|
2019-05-14 14:07:36 +08:00 |
|
|
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351d5360f0
|
llvm -> llvm_7 for nixos-unstable rustc
|
2019-05-14 10:41:10 +08:00 |
|
|
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f7e7b894b7
|
simplesoc_ecp5: disable minerva muldiv
|
2019-05-13 00:46:52 +08:00 |
|
|
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52f663eda6
|
minerva: bump
|
2019-05-13 00:46:43 +08:00 |
|
|
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05822f0a36
|
simplesoc_ecp5: remove nmigen/#30 workaround
|
2019-05-12 15:01:45 +08:00 |
|
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c77c296e72
|
nmigen: bump
|
2019-05-12 14:58:08 +08:00 |
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e74b5dfe00
|
ecp5: use speed grade 8 (versa)
|
2019-05-06 22:44:58 +08:00 |
|
|
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7ffce5882e
|
add simplesoc_ecp5 to continuous build
|
2019-05-02 12:54:57 +08:00 |
|
|
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5bc9189709
|
add simplesoc_ecp5 (WIP)
|
2019-05-02 12:53:28 +08:00 |
|
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70638e6d87
|
add wishbone components
|
2019-05-02 12:53:08 +08:00 |
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88db84cfd7
|
uart: style
|
2019-05-02 12:52:29 +08:00 |
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d765dfb7b9
|
add __all__
|
2019-05-01 17:05:19 +08:00 |
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d84b172245
|
helloworld_ecp5: add delays between messages
Otherwise the FTDI UART goes out of sync and corrupts data.
|
2019-04-30 15:52:41 +08:00 |
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1cf460b56f
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helloworld_ecp5: fix serial_tx location
|
2019-04-30 13:36:09 +08:00 |
|
Charles Papon
|
7d227ba4c5
|
Update to SpinalHDL 1.3.3 VexRiscv 1.1
|
2019-04-28 20:49:45 +08:00 |
|
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83bbf62f04
|
nmigen: bump
|
2019-04-27 15:00:07 +08:00 |
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73ef6dcfe8
|
yosys: update version number
|
2019-04-27 14:59:16 +08:00 |
|
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4052e4ff93
|
yosys: bump
|
2019-04-27 14:45:05 +08:00 |
|
|
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fe7ee7b58d
|
helloworld_ecp5: fix LPF
|
2019-04-27 14:39:34 +08:00 |
|
|
|
263b04245e
|
add continuous build for helloworld examples
|
2019-04-26 18:27:06 +08:00 |
|
|
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5436920008
|
add ECP5 helloworld
|
2019-04-26 18:22:23 +08:00 |
|
