M-Labs/HeavyX
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Next-generation FPGA SoC toolkit
79 Commits 2 Branches 0 Tags 412 KiB
Nix 60.4%
Python 29.9%
Diff 7.1%
Rust 2.4%
RPC 0.2%
78f67f82d3
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Sebastien Bourdeauducq 78f67f82d3 firmware: simulable demo 
Run:
qemu-system-riscv32 -nographic -machine sifive_u -kernel target/riscv32imc-unknown-none-elf/release/helloworld
2019-06-06 10:33:29 +08:00
compilers binutils: use unknown-elf 2019-06-06 00:06:29 +08:00
cores minerva: bump 2019-05-25 12:23:17 +08:00
eda nmigen: bump 2019-05-15 18:55:32 +08:00
examples simplesoc_ecp5: disable minerva muldiv 2019-05-13 00:46:52 +08:00
firmware firmware: simulable demo 2019-06-06 10:33:29 +08:00
heavycomps add wishbone components 2019-05-02 12:53:08 +08:00
.gitignore add nix-build results to .gitignore 2019-03-25 23:36:52 +08:00
default.nix add ECP5 helloworld 2019-04-26 18:22:23 +08:00
derivations.nix use the GNU linker 2019-06-06 00:07:53 +08:00
heavycomps.nix add component library with UART 2019-03-19 16:52:02 +08:00
release.nix add simplesoc_ecp5 to continuous build 2019-05-02 12:54:57 +08:00
shell-firmware.nix use the GNU linker 2019-06-06 00:07:53 +08:00