Commit Graph

123 Commits

Author SHA1 Message Date
1361c6ae9e Revert "llvm: only build x86 and riscv"
This reverts commit b17ec6fb1f.
2019-06-05 23:41:22 +08:00
b17ec6fb1f llvm: only build x86 and riscv
Attempting to fix llvm-lld breakage on msp430 by disabling msp430.
2019-06-05 23:19:51 +08:00
52cc7722a0 add nix-shell file for firmware compilation 2019-06-05 23:08:55 +08:00
6ad1d993c6 rustc: remove riscv32i support 2019-06-05 23:07:49 +08:00
f929be260a build cargo 2019-06-05 23:06:57 +08:00
2c3fc22963 Use riscv32imc for Rust core crate
Some other crates have issues with riscv32i.
2019-06-05 23:06:03 +08:00
14c7b4890c rustc: enable lld 2019-06-05 23:05:15 +08:00
d02da47167 minerva: bump 2019-05-25 12:23:17 +08:00
2f3c1824a6 nmigen: bump 2019-05-15 18:55:32 +08:00
ec09c09cf3 rust-riscv32i-crates: use external compiler_builtins 2019-05-14 20:35:40 +08:00
a0690fe0e2 rust-riscv32i-crates: disable compiler_builtins 2019-05-14 19:58:13 +08:00
9e93a9cf39 rustc: make llvm override compatible with nixos-unstable 2019-05-14 19:17:16 +08:00
9f4538555e fix previous commit 2019-05-14 19:16:52 +08:00
e9b005d50a mark riscv rustc 2019-05-14 19:05:30 +08:00
677ddefff2 mark riscv llvm 2019-05-14 14:07:36 +08:00
351d5360f0 llvm -> llvm_7 for nixos-unstable rustc 2019-05-14 10:41:10 +08:00
f7e7b894b7 simplesoc_ecp5: disable minerva muldiv 2019-05-13 00:46:52 +08:00
52f663eda6 minerva: bump 2019-05-13 00:46:43 +08:00
05822f0a36 simplesoc_ecp5: remove nmigen/#30 workaround 2019-05-12 15:01:45 +08:00
c77c296e72 nmigen: bump 2019-05-12 14:58:08 +08:00
e74b5dfe00 ecp5: use speed grade 8 (versa) 2019-05-06 22:44:58 +08:00
7ffce5882e add simplesoc_ecp5 to continuous build 2019-05-02 12:54:57 +08:00
5bc9189709 add simplesoc_ecp5 (WIP) 2019-05-02 12:53:28 +08:00
70638e6d87 add wishbone components 2019-05-02 12:53:08 +08:00
88db84cfd7 uart: style 2019-05-02 12:52:29 +08:00
d765dfb7b9 add __all__ 2019-05-01 17:05:19 +08:00
d84b172245 helloworld_ecp5: add delays between messages
Otherwise the FTDI UART goes out of sync and corrupts data.
2019-04-30 15:52:41 +08:00
1cf460b56f helloworld_ecp5: fix serial_tx location 2019-04-30 13:36:09 +08:00
Charles Papon
7d227ba4c5 Update to SpinalHDL 1.3.3 VexRiscv 1.1 2019-04-28 20:49:45 +08:00
83bbf62f04 nmigen: bump 2019-04-27 15:00:07 +08:00
73ef6dcfe8 yosys: update version number 2019-04-27 14:59:16 +08:00
4052e4ff93 yosys: bump 2019-04-27 14:45:05 +08:00
fe7ee7b58d helloworld_ecp5: fix LPF 2019-04-27 14:39:34 +08:00
263b04245e add continuous build for helloworld examples 2019-04-26 18:27:06 +08:00
5436920008 add ECP5 helloworld 2019-04-26 18:22:23 +08:00
3b2f6a222e cleanup 2019-04-26 17:43:31 +08:00
40eced0136 vivado.nix: revert accidentally committed part 2019-04-26 17:01:26 +08:00
86e0299200 helloworld_kintex7: fix 2019-04-26 16:59:19 +08:00
a19f0784d0 use Elaboratable 2019-04-26 16:57:59 +08:00
347e858ece helloworld -> helloworld_kintex7 2019-04-26 16:56:47 +08:00
05974f272d bump minerva 2019-04-22 14:40:17 +08:00
dd64f92754 bump nmigen 2019-04-22 14:40:04 +08:00
2bd819fcbe roundrobin: use nmigen zero-width signals 2019-04-18 11:58:51 +08:00
e14031fba6 add round-robin arbiter 2019-04-17 20:18:41 +08:00
034ecc4d99 nmigen: run tests in verbose mode 2019-04-17 16:08:37 +08:00
4dd024942e nmigen: bump 2019-04-17 16:08:18 +08:00
e3f47815e5 rust: add riscv32i 2019-04-09 00:48:19 +08:00
25fe837684 use upstream rust/llvm 2019-04-09 00:09:58 +08:00
c3992220e5 rustc: fix crates compilation 2019-04-07 23:16:00 +08:00
da982a60cc rustc: add libxml2 dep 2019-04-07 00:45:02 +08:00