14e09582b6
wrpll: work around si549 not working when lsdiv=2
2019-12-09 16:20:08 +08:00
439576f59d
wrpll: fix Si549 initialization delays
2019-12-09 16:13:57 +08:00
0499f83580
wrpll: helper clock sanity check
2019-12-08 23:46:33 +08:00
Paweł Kulik
14e250c78f
Enabled internal pullup for CML SYSREF outputs, otherwise there is no signal on them.
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Signed-off-by: Paweł Kulik <pawel.kulik@creotech.pl>
2019-12-07 09:30:24 +08:00
eb271f383b
wrpll: add DDMTD cores
2019-11-28 22:03:50 +08:00
39d5ca11f4
si549: increase I2C frequency
2019-11-28 22:03:26 +08:00
87894102e5
si549: use recommended i2c read sequence
2019-11-28 17:49:02 +08:00
354d82cfe3
wrpll: drive helper clock domain
2019-11-28 17:40:00 +08:00
68cab5be8c
si549: cleanups
2019-11-28 16:36:59 +08:00
bcd2383c9d
wrpll: si549 initialization
2019-11-27 22:58:08 +08:00
4832bfb08c
wrpll: i2c functions, select_recovered_clock placeholder
2019-11-27 21:21:00 +08:00
449d2c4f08
libboard_misoc: fix !has_i2c
2019-11-27 21:04:28 +08:00
e0687b77f5
si5324: 10 MHz ext_ref_frequency
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* close #1254
* tested on innsbruck2 kasli variant
* sponsored by Uni Innsbruck/AQT
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-11-22 18:29:12 +01:00
6644903843
bootloader: fix imports
2019-11-06 14:45:55 +08:00
b25a17fa37
netboot: support slave FPGA loading
2019-11-05 16:28:49 +08:00
9dc82bd766
bootloader: add no_flash_boot config option to force network boot
2019-11-05 15:31:08 +08:00
29b4d87943
firmware: add cargosha256.nix
2019-11-01 10:28:41 +08:00
5362f92b39
bootloader: disable minimum stack space check in linker script
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* The value varies greatly whether netboot is enabled or not.
* There is no simple solution to detect has_ethmac in the linker script and set the value accordingly.
* The space check is an imperfect solution that will be superseded by stack pointer limits.
* Left commented out so we can re-enable it manually during development if stack corruption is suspected.
2019-11-01 10:25:14 +08:00
deadfead2a
bootloader: fix !has_ethmac
2019-11-01 10:19:08 +08:00
a78e493b72
firmware: load slave FPGA in bootloader
2019-10-31 12:42:40 +08:00
389a8f587a
slave_fpga: modularize
2019-10-31 11:50:53 +08:00
bc050fdeec
bootloader: treat zero-length firmware in flash as no firmware
2019-10-30 21:46:06 +08:00
462cf5967e
bootloader: add netboot support
2019-10-30 21:23:42 +08:00
f2f7170d20
hmc7043: use recommend I/O standards
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https://github.com/sinara-hw/Sayma_RTM/issues/116#issuecomment-544187952
2019-10-21 22:56:10 +08:00
47a83c71f1
firmware: more readable network addresses message
2019-10-21 14:00:14 +08:00
818d6b2f5a
bootloader: fix compilation problems
2019-10-21 13:28:17 +08:00
8f76a3218e
firmware: move i2c to libboard_misoc, enable IPv6 in bootloader, share network settings
2019-10-21 12:58:52 +08:00
1c5e749036
satman: remove compilation warning without JESD DACs
2019-10-21 12:53:54 +08:00
d26d80410e
runtime: refactor network settings
2019-10-19 17:56:35 +08:00
6d5dcb4211
runtime: enable IPv6. Closes #349
2019-10-19 17:20:33 +08:00
05e8f24c24
sayma2: JESD204 synchronization
2019-10-18 23:28:47 +08:00
4df2c5d1fb
sayma: prepare for SYSREF align
...
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
2019-10-08 12:30:47 +08:00
5ee81dc643
satman: define constants for JdacBasicRequest reqnos
2019-10-08 10:27:04 +08:00
4b3baf4825
firmware: run PRBS and STPL JESD204 tests
2019-10-08 00:10:36 +08:00
ebd5d890f1
satman: check for JESD ready
2019-10-06 23:10:57 +08:00
90e3b83e80
hmc7043: turn on AMC_FPGA_SYSREF1
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Florent's JESD core won't work at all without.
2019-10-06 22:49:00 +08:00
1bc7743e03
sayma: fix hmc7043 output settings for v2 hardware
2019-10-06 21:50:29 +08:00
a421820a32
sayma: initialize DACs over DRTIO
2019-10-06 21:42:45 +08:00
f8e4cc37d0
sayma_rtm: reset and detect DACs
2019-10-06 20:15:27 +08:00
f62dc7e1d4
sayma: refactor JESD DAC channel groups
2019-10-06 20:15:09 +08:00
c4c884b8ce
ad9154: simplify, focus on AD9154 config and do not include JESD
2019-10-06 20:07:02 +08:00
fdba0bfbbc
satman: move now-unrelated hmc830_7043 init away from DRTIO transceiver init
2019-10-06 19:22:46 +08:00
ad63908aff
hmc830_7043: enable_fpga_ibuf -> unmute
2019-10-06 18:13:59 +08:00
5ad65b9d30
hmc830_7043: remove clock_mux
2019-10-06 18:13:27 +08:00
e9b81f6e33
remove serwb
...
DRTIO is a better solution
2019-10-06 18:10:23 +08:00
4e77be0511
firmware: add Cargo.lock header that newer cargo wants
2019-09-17 15:22:14 +08:00
David Nadlinger
6d6f66338b
runtime: Update core config panic_reset command suggestion message
2019-09-10 19:31:19 +01:00
90e8e074cd
firmware: turn errors into &str for remote_i2c as well
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should resolve breakage on a few targets/variants introduced by PR #1351
2019-08-29 09:05:47 +08:00
71b3c66af9
firmware: conditionally compile has_si5324
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avoids unused warnings where this module is not used.
2019-08-29 09:04:54 +08:00
afe162ceca
firmware: don't unwrap() but propagate pca9548 errors
2019-08-17 09:15:26 +08:00
a8aabd3815
firwmare: turn i2c errors into &str
2019-08-17 09:15:26 +08:00
8fc5ce902f
firmware: let kasli obtain default hardware_addr from i2c_eeprom
2019-08-17 09:15:26 +08:00
d666f3d573
firmware: factor out mod pca9548 from si5324
...
orepares for further i2c devices.
2019-08-17 09:15:26 +08:00
5a9bb0ecba
runtime: fix incorrect 'RTIO clock failed' report
2019-06-24 23:33:13 +08:00
whitequark
b8b9fa51bd
libdyld: accept objects with no rela relocations.
2019-06-17 06:43:34 +00:00
53c778ae2d
runtime: fix previous commit
2019-06-14 15:53:01 +08:00
a947867887
runtime: support Kasli Si5324 bypass via rtio_clock=e
2019-06-14 15:48:05 +08:00
66a66b03b4
style
2019-06-14 15:29:16 +08:00
87ce24e867
runtime: refactor startup and RTIO clocking initialization
2019-06-14 15:26:30 +08:00
43e58c939c
sayma: drop MasterDAC
...
This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.
Now Sayma works fine with Kasli as a master, which is simpler.
2019-06-14 14:06:16 +08:00
b04e15741b
drop SI5324_SAYMA_REF
2019-06-14 14:03:48 +08:00
874542f33f
add Metlino support
2019-05-19 10:57:43 +08:00
David Nadlinger
4d215cf541
firmware: Add Si5324 config for 125 MHz ext ref
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PLL divider settings as suggested by DSPLLsim 5.1.
2019-04-15 22:22:19 +01:00
David Nadlinger
cd7a5a3683
firmware: Fix kernel RPC handling of zero-size values (e.g. empty arrays)
2019-03-31 18:33:44 +01:00
David Nadlinger
b4ddf4c86b
firmware: Make "unexpected reply from kernel CPU" log messages unique
...
This makes it easier to localize issues based on the log output.
2019-03-31 18:31:56 +01:00
David Nadlinger
8e225433a5
firmware: Fix kernel RPC strings size (memory corruption)
...
Test case to follow.
2019-03-31 17:10:27 +01:00
David Nadlinger
b8ff627be9
firmware: Fix kernel RPC tuple size calculation (memory corruption)
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Test case to follow.
2019-03-31 17:10:27 +01:00
c7205ad82f
sayma_rtm: preliminary v2 support
2019-03-23 12:37:03 +08:00
b56c7cec1e
kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target
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Urukul sync is not reliable at 125/1000
2019-02-05 11:24:45 +08:00
ec230d6560
sayma: move SYSREF DDMTD to the RTM
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Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
2019-01-31 20:39:33 +08:00
82106dcd95
si5324: add bypass function
2019-01-31 19:38:55 +08:00
8bbd4207d8
si5324: use consistent bitmask
2019-01-31 19:35:56 +08:00
d3c608aaec
jesd204sync: reset and check lock status of DDMTD helper PLL in firmware
2019-01-31 15:11:16 +08:00
fa3b40141d
hmc830_7043: document sayma clock muxes
2019-01-31 15:10:11 +08:00
ec8560911f
siphaser: bugfixes
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* Fix integer overflow in degree computation
* Add some phase slips after the first transition to get out of the jitter zone and avoid intermittent short windows
2019-01-30 16:56:38 +08:00
c591009220
sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler
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Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
2019-01-29 23:30:01 +08:00
9d0d02a561
jesd204sync: increase tolerance for coarse->final target in calibrate_sysref_target
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There is plenty of slack (it only needs to meet timing at the RTIO frequency).
2019-01-29 16:48:55 +08:00
ed6aa29897
jesd204sync: print more information on test_slip_ddmtd error
2019-01-29 16:47:29 +08:00
7a5d28b73d
jesd204sync: test SYSREF period
2019-01-28 19:11:38 +08:00
1a42e23fb4
jesd204sync: print DDMTD SYSREF final alignment delta
2019-01-28 18:39:16 +08:00
eebff6d77f
jesd204sync: fix max_phase_deviation
2019-01-28 18:38:18 +08:00
b9e3fab49c
jesd204sync: improve messaging
2019-01-28 18:37:46 +08:00
145f08f3fe
jesd204sync: update SYSREF S/H limit deviation tolerance
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Follows the increased DDMTD resolution.
2019-01-28 18:21:31 +08:00
ba21dc8498
jesd204sync: improve messaging
2019-01-28 18:08:20 +08:00
3acee87df2
firmware: improve DDMTD resolution using dithering/averaging
2019-01-28 16:04:04 +08:00
cfe66549ff
jesd204sync: cleanup DDMTD averaging code
2019-01-28 14:14:50 +08:00
2b0d63db23
hmc830_7043: support 125MHz RTIO
2019-01-28 13:44:08 +08:00
bdd4e52a53
ad9154: support 125MHz RTIO
2019-01-28 13:43:52 +08:00
3b6f47886e
firmware: print more info on DDMTD stability error
2019-01-27 23:06:11 +08:00
74fdd04622
firmware: test DDMTD stability
2019-01-27 20:39:12 +08:00
8254560577
sayma: properly determine SYSREF coarse calibration target
2019-01-27 16:00:36 +08:00
214394e3b0
sayma: reimplement DAC SYSREF autocalibration
2019-01-27 15:28:39 +08:00
fdbf1cc2b2
sayma: rework DAC SYSREF margin validation
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Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
2019-01-27 14:17:54 +08:00
7e5c062c2c
firmware: bypass channel divider for HMC7043 DCLK
2019-01-27 11:49:34 +08:00
f73ffe44f9
firmware: implement DDMTD-based SYSREF/RTIO alignment (draft)
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Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO.
Needs cleanup and optimization/characterization.
2019-01-27 09:51:24 +08:00
cb04230f86
sayma: SYSREF setup/hold validation demonstration
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This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
2019-01-25 16:58:58 +08:00
3356717316
sayma: DDMTD SYSREF measurement demonstration
2019-01-25 16:00:31 +08:00
4941fb3300
sayma: 2.4GHz DAC clocking (4X interpolation)
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* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
2019-01-25 13:47:04 +08:00
cc9420d2c8
hmc7043: fix divider programming
2019-01-25 11:48:50 +08:00
bbac92442f
sayma: check hmc7043 slip period
2019-01-24 20:13:43 +08:00
