forked from M-Labs/artiq
runtime: refactor startup and RTIO clocking initialization
This commit is contained in:
parent
43e58c939c
commit
87ce24e867
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@ -41,6 +41,7 @@ use proto_artiq::{mgmt_proto, moninj_proto, rpc_proto, session_proto, kernel_pro
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#[cfg(has_rtio_analyzer)]
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use proto_artiq::analyzer_proto;
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mod rtio_clocking;
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mod rtio_mgt;
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mod urc;
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@ -59,14 +60,15 @@ mod moninj;
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#[cfg(has_rtio_analyzer)]
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mod analyzer;
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fn startup() {
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irq::set_mask(0);
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irq::set_ie(true);
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clock::init();
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info!("ARTIQ runtime starting...");
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info!("software ident {}", csr::CONFIG_IDENTIFIER_STR);
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info!("gateware ident {}", ident::read(&mut [0; 64]));
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#[cfg(has_grabber)]
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fn grabber_thread(io: sched::Io) {
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loop {
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board_artiq::grabber::tick();
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io.sleep(200).unwrap();
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}
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}
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fn setup_log_levels() {
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match config::read_str("log_level", |r| r.map(|s| s.parse())) {
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Ok(Ok(log_level_filter)) => {
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info!("log level set to {} by `log_level` config key",
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@ -84,30 +86,14 @@ fn startup() {
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}
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_ => info!("UART log level set to INFO by default")
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}
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}
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fn sayma_hw_init() {
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#[cfg(has_slave_fpga_cfg)]
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board_artiq::slave_fpga::load().expect("cannot load RTM FPGA gateware");
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#[cfg(has_serwb_phy_amc)]
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board_artiq::serwb::wait_init();
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#[cfg(has_uart)] {
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let t = clock::get_ms();
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info!("press 'e' to erase startup and idle kernels...");
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while clock::get_ms() < t + 1000 {
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if unsafe { csr::uart::rxtx_read() == b'e' } {
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config::remove("startup_kernel").unwrap();
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config::remove("idle_kernel").unwrap();
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info!("startup and idle kernels erased");
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break
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}
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}
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info!("continuing boot");
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}
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#[cfg(has_i2c)]
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board_artiq::i2c::init();
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#[cfg(si5324_as_synthesizer)]
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setup_si5324_as_synthesizer();
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#[cfg(has_hmc830_7043)]
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/* must be the first SPI init because of HMC830 SPI mode selection */
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board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
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@ -124,98 +110,22 @@ fn startup() {
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}
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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#[cfg(has_ethmac)]
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startup_ethernet();
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#[cfg(not(has_ethmac))]
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{
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info!("done");
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loop {}
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}
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}
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#[cfg(si5324_as_synthesizer)]
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fn setup_si5324_as_synthesizer()
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{
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// 125MHz output, from 100MHz CLKIN2 reference, 586 Hz loop bandwidth
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 260,
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n31 : 65,
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n32 : 52,
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bwsel : 4,
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crystal_ref: false
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};
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// 125MHz output, from 125MHz CLKIN2 reference, 606 Hz loop bandwidth
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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n2_hs : 7,
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n2_ls : 360,
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n31 : 63,
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n32 : 63,
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bwsel : 4,
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crystal_ref: false
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};
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// 125MHz output, from crystal, 7 Hz
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#[cfg(all(rtio_frequency = "125.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4993,
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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};
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// 150MHz output, from crystal
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#[cfg(all(rtio_frequency = "150.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 9370,
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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};
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// 100MHz output, from crystal. Also used as reference for Sayma HMC830.
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#[cfg(all(rtio_frequency = "100.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 6,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 9370,
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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};
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board_artiq::si5324::setup(&SI5324_SETTINGS,
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board_artiq::si5324::Input::Ckin2).expect("cannot initialize Si5324");
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}
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fn startup() {
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irq::set_mask(0);
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irq::set_ie(true);
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clock::init();
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info!("ARTIQ runtime starting...");
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info!("software ident {}", csr::CONFIG_IDENTIFIER_STR);
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info!("gateware ident {}", ident::read(&mut [0; 64]));
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#[cfg(has_grabber)]
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fn grabber_thread(io: sched::Io) {
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loop {
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board_artiq::grabber::tick();
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io.sleep(200).unwrap();
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}
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}
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setup_log_levels();
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#[cfg(has_i2c)]
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board_artiq::i2c::init();
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sayma_hw_init();
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rtio_clocking::init();
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#[cfg(has_ethmac)]
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fn startup_ethernet() {
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let hardware_addr;
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match config::read_str("mac", |r| r.map(|s| s.parse())) {
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Ok(Ok(addr)) => {
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@ -0,0 +1,162 @@
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use board_misoc::config;
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#[cfg(si5324_as_synthesizer)]
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use board_artiq::si5324;
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#[cfg(has_drtio)]
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use board_misoc::csr;
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#[derive(Debug)]
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pub enum RtioClock {
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Internal = 0,
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External = 1
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}
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fn get_rtio_clock_cfg() -> RtioClock {
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config::read("rtio_clock", |result| {
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match result {
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Ok(b"i") => {
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info!("using internal RTIO clock");
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RtioClock::Internal
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},
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Ok(b"e") => {
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info!("using external RTIO clock");
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RtioClock::External
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},
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_ => {
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info!("using internal RTIO clock (by default)");
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RtioClock::Internal
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},
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}
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})
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}
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#[cfg(has_rtio_crg)]
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pub mod crg {
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#[cfg(has_rtio_clock_switch)]
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use super::RtioClock;
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use board_misoc::{clock, csr};
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pub fn check() -> bool {
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unsafe { csr::rtio_crg::pll_locked_read() != 0 }
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}
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#[cfg(has_rtio_clock_switch)]
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pub fn init(clk: RtioClock) -> bool {
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unsafe {
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csr::rtio_crg::pll_reset_write(1);
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csr::rtio_crg::clock_sel_write(clk as u8);
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csr::rtio_crg::pll_reset_write(0);
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}
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clock::spin_us(150);
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return check()
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}
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#[cfg(not(has_rtio_clock_switch))]
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pub fn init() -> bool {
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unsafe {
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csr::rtio_crg::pll_reset_write(0);
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}
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clock::spin_us(150);
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return check()
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}
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}
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#[cfg(not(has_rtio_crg))]
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pub mod crg {
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pub fn check() -> bool { true }
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}
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#[cfg(si5324_as_synthesizer)]
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fn setup_si5324_as_synthesizer() {
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// 125MHz output, from 100MHz CLKIN2 reference, 586 Hz loop bandwidth
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 260,
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n31 : 65,
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n32 : 52,
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bwsel : 4,
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crystal_ref: false
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};
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// 125MHz output, from 125MHz CLKIN2 reference, 606 Hz loop bandwidth
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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n2_hs : 7,
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n2_ls : 360,
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n31 : 63,
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n32 : 63,
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bwsel : 4,
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crystal_ref: false
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};
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// 125MHz output, from crystal, 7 Hz
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#[cfg(all(rtio_frequency = "125.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4993,
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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};
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// 150MHz output, from crystal
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#[cfg(all(rtio_frequency = "150.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 9370,
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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};
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// 100MHz output, from crystal. Also used as reference for Sayma HMC830.
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#[cfg(all(rtio_frequency = "100.0", not(si5324_ext_ref)))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 6,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 9370,
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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};
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si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin2).expect("cannot initialize Si5324");
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}
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pub fn init() {
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#[cfg(si5324_as_synthesizer)]
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setup_si5324_as_synthesizer();
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#[cfg(has_drtio)]
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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#[cfg(has_rtio_crg)]
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{
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#[cfg(has_rtio_clock_switch)]
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{
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if !crg::init(get_rtio_clock_cfg()) {
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error!("RTIO clock failed");
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}
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}
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#[cfg(not(has_rtio_clock_switch))]
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{
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if !crg::init() {
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error!("RTIO clock failed");
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}
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}
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}
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}
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@ -3,46 +3,10 @@ use urc::Urc;
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use board_misoc::csr;
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#[cfg(has_drtio)]
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use board_misoc::clock;
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#[cfg(has_rtio_clock_switch)]
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use board_misoc::config;
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use board_artiq::drtio_routing;
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use sched::Io;
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use sched::Mutex;
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#[cfg(has_rtio_crg)]
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pub mod crg {
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use board_misoc::{clock, csr};
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pub fn check() -> bool {
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unsafe { csr::rtio_crg::pll_locked_read() != 0 }
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}
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#[cfg(has_rtio_clock_switch)]
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pub fn init(clk: u8) -> bool {
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unsafe {
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csr::rtio_crg::pll_reset_write(1);
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csr::rtio_crg::clock_sel_write(clk);
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csr::rtio_crg::pll_reset_write(0);
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}
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clock::spin_us(150);
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return check()
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}
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#[cfg(not(has_rtio_clock_switch))]
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pub fn init() -> bool {
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unsafe {
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csr::rtio_crg::pll_reset_write(0);
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}
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clock::spin_us(150);
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return check()
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}
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}
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#[cfg(not(has_rtio_crg))]
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pub mod crg {
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pub fn check() -> bool { true }
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}
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#[cfg(has_drtio)]
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pub mod drtio {
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use super::*;
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@ -51,9 +15,6 @@ pub mod drtio {
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pub fn startup(io: &Io, aux_mutex: &Mutex,
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routing_table: &Urc<RefCell<drtio_routing::RoutingTable>>,
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up_destinations: &Urc<RefCell<[bool; drtio_routing::DEST_COUNT]>>) {
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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let aux_mutex = aux_mutex.clone();
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let routing_table = routing_table.clone();
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let up_destinations = up_destinations.clone();
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@ -380,52 +341,10 @@ fn async_error_thread(io: Io) {
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pub fn startup(io: &Io, aux_mutex: &Mutex,
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routing_table: &Urc<RefCell<drtio_routing::RoutingTable>>,
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up_destinations: &Urc<RefCell<[bool; drtio_routing::DEST_COUNT]>>) {
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// The RTIO CRG may depend on the DRTIO transceiver clock.
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// Initialize DRTIO first to bring up transceiver clocking.
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drtio::startup(io, aux_mutex, routing_table, up_destinations);
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#[cfg(has_rtio_crg)]
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{
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#[cfg(has_rtio_clock_switch)]
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{
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#[derive(Debug)]
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enum RtioClock {
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Internal = 0,
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External = 1
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};
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let clk = config::read("rtio_clock", |result| {
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match result {
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Ok(b"i") => {
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info!("using internal RTIO clock");
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RtioClock::Internal
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},
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Ok(b"e") => {
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info!("using external RTIO clock");
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RtioClock::External
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},
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_ => {
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info!("using internal RTIO clock (by default)");
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RtioClock::Internal
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},
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}
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});
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if !crg::init(clk as u8) {
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error!("RTIO clock failed");
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}
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}
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#[cfg(not(has_rtio_clock_switch))]
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{
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if !crg::init() {
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error!("RTIO clock failed");
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}
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}
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}
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unsafe {
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csr::rtio_core::reset_phy_write(1);
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}
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io.spawn(4096, async_error_thread);
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}
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@ -7,7 +7,7 @@ use board_misoc::{ident, cache, config};
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use {mailbox, rpc_queue, kernel};
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use urc::Urc;
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use sched::{ThreadHandle, Io, Mutex, TcpListener, TcpStream, Error as SchedError};
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use rtio_mgt;
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use rtio_clocking;
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use rtio_dma::Manager as DmaManager;
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use cache::Cache;
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use kern_hwreq;
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@ -527,7 +527,7 @@ fn host_kernel_worker(io: &Io, aux_mutex: &Mutex,
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return Err(Error::WatchdogExpired(idx))
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}
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if !rtio_mgt::crg::check() {
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if !rtio_clocking::crg::check() {
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host_write(stream, host::Reply::ClockFailure)?;
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return Err(Error::ClockFailure)
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}
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|
@ -571,7 +571,7 @@ fn flash_kernel_worker(io: &Io, aux_mutex: &Mutex,
|
|||
return Err(Error::WatchdogExpired(idx))
|
||||
}
|
||||
|
||||
if !rtio_mgt::crg::check() {
|
||||
if !rtio_clocking::crg::check() {
|
||||
return Err(Error::ClockFailure)
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue