forked from M-Labs/artiq
hmc830_7043: document sayma clock muxes
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@ -9,10 +9,10 @@ mod clock_mux {
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pub fn init() {
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unsafe {
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csr::clock_mux::out_write(
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1*CLK_SRC_EXT_SEL | // use ext clk from sma
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1*REF_CLK_SRC_SEL |
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1*DAC_CLK_SRC_SEL |
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0*REF_LO_CLK_SEL);
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1*CLK_SRC_EXT_SEL | // 1= ext clk from sma, 0= RF backplane (IC46) to IC45
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1*REF_CLK_SRC_SEL | // 1= low-noise clock, 0= Si5324 output (IC45) to HMC830
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1*DAC_CLK_SRC_SEL | // 1= HMC830 output, 1= clock mezzanine (IC54) to HMC7043 and J58/J59
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0*REF_LO_CLK_SEL); // 1= clock mezzanine, 0= HMC830 input (IC52) to AFEs and J56/J57
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}
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}
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}
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