Commit Graph

45 Commits

Author SHA1 Message Date
191eacdf8c HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout; LVDS&IO: fix name issue 2021-07-09 14:36:13 +08:00
f9574a2098 HSADC: reselect new op amp 2021-07-07 17:26:54 +08:00
3228e16c8f MCU, FPGA, Ethernet, PCB: fix decoupling capacitors 2021-07-07 16:14:10 +08:00
90053d4887 PowerSupply: fix TVS protection bug; PCB: finish routing 2021-07-06 15:41:17 +08:00
eceba52792 PCB & FPGA & MCU: fix LVDS impedance issues 2021-07-06 10:28:18 +08:00
1b592eed37 FPGA & MCU & PCB: add decoupling capactors 2021-07-02 11:04:53 +08:00
f796eedc08 PCB: fix grand dead zones 2021-06-30 15:24:25 +08:00
4853b02184 PCB: replace 0201 resistors to 0402 as JLC cannot do SMT for 0201 2021-06-30 14:59:13 +08:00
93ba0cbe9d HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout 2021-06-30 14:51:30 +08:00
17127387c9 PCB: optimize buck converter and shunt resistor layout 2021-06-30 11:36:53 +08:00
26d727f8c5 PCB: replace LVDS resistors with 0201 package, optimize LVDS pairs layout 2021-06-29 16:49:26 +08:00
8ffd698079 PCB: optimize HSADC layout 2021-06-29 10:38:12 +08:00
6584f44f2a PCB: fix GND polygon dead zones; all: export BOM 2021-06-29 10:26:02 +08:00
10818a4771 PCB: fix small LVDS connection issue 2021-06-28 15:49:33 +08:00
a16bee581b PCB: fix small LVDS connection issue 2021-06-28 15:45:06 +08:00
185f9eacda PCB: finish routing 2021-06-28 15:40:16 +08:00
53accc8761 PCB: finish IO and analog connectors 2021-06-28 10:40:21 +08:00
4b15f466a0 PCB: finish SWD, IIC 2021-06-25 18:15:56 +08:00
0e1120d266 FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing 2021-06-25 16:57:46 +08:00
2a31c8b3f3 PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
37941bfc2c PCB: finalize component positions and define board shape 2021-06-22 17:14:32 +08:00
6535ff5423 LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout 2021-06-22 16:34:02 +08:00
1df738664f all: update gitignore; remove redundant files 2021-06-22 09:44:50 +08:00
b740887ac2 HighSpeedADC: fix chip rotation bug, remove SMA connector; all: fix BJT base resistors; Power: remove DC jack; LVDS&IO: replace IDC header with dupont 2021-06-21 17:06:36 +08:00
982fefd6b5 all: update gitigore to fix symbol and footpin bugs; replace messy libs into one 2021-06-21 16:05:17 +08:00
327abdeb24 CurrentSensor: fix bugs and replace opamp with current senser 2021-06-21 15:10:25 +08:00
9bcc9a229b TestAutomation: replace messy wires with bus 2021-06-21 12:10:31 +08:00
45940c1ac8 all: finish routing 2021-06-18 16:13:42 +08:00
9c10edde19 CurrentSensor: add mid point voltage reference; FPGA: fix pinout 2021-06-18 14:24:15 +08:00
0cebd6ed2b LVDS: add LVDS ports; all: add LEDs 2021-06-18 11:30:16 +08:00
74f4fc201a FPGA: add GPIO and ADC parallel port 2021-06-18 10:27:05 +08:00
9a62476f9e MCU: finish connectors 2021-06-17 17:33:12 +08:00
4123caa996 all: add gitignore; remove redundant files from repo; optimize file name style 2021-06-17 15:49:24 +08:00
6cee2d0419 Current_Senser: add current sampling; all: optimize +3.3VA 2021-06-17 15:30:51 +08:00
9f7ffb7754 docs: remove unused Chinese docs 2021-06-17 11:12:40 +08:00
dfe4255a21 MCU: finish FSMC, PWM 2021-06-17 10:52:33 +08:00
fc8c667020 Power: fix hierarchical and global label 2021-06-16 17:32:33 +08:00
5b4801ff74 FPGA: finish EEM, I2C, CFG, SPI FLASH 2021-06-16 17:32:33 +08:00
fc2cb47610 all: map symbol and footpins 2021-06-16 17:32:33 +08:00
24471104a5 Analog_LVDS: finish ADC 2021-06-16 17:32:33 +08:00
66188cd3ad Ethernet: finish ethernet controller and PoE input 2021-06-16 17:32:33 +08:00
e28d01d115 PowerSupply: finish power supply part: 12V --(DCDC)--> 6.5V --(LDO)--> 5V+3.3V+2.5V+1.2V 2021-06-16 17:32:33 +08:00
83bc618f77 PowerSupply: finish PoE and 12V input schematic 2021-06-16 17:32:32 +08:00
232af06c28 components confirmed; datasheet collected; framework finished 2021-06-16 17:32:32 +08:00
da19dad9cd init project 2021-06-16 17:31:36 +08:00