Sebastien Bourdeauducq
7b72c9e915
remove WRPLL
2022-07-08 17:55:26 +08:00
mwojcik
f281112779
satman: add 100mhz si5324 settings
...
siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
mwojcik
eec3ea6589
siphaser: add support for 100mhz rtio
2021-12-03 17:19:11 +08:00
occheung
c6e0e26440
drtio: accept 32b/64b bus
2021-11-08 16:59:08 +08:00
mwojcik
7879d3630b
made kc705/gtx interface more similar to kasli/gtp
2021-08-10 18:53:52 +08:00
Harry Ho
a0fd5261ea
kc705: cleanup
2021-01-22 11:11:13 +08:00
Harry Ho
88b14082b6
drtio/transceiver/gtx: delete obsolete modules
2021-01-20 15:05:32 +08:00
Harry Ho
52afd4ef6b
kc705: add GTX multilane support, add multichannel support on master
...
* One DRTIO master channel is enabled by default.
* User can set the SMA as the 2nd master channel (by passing --drtio-sma to the argparser).
* Multi-channel (i.e. with repeaters) on KC705 satellite is supported but has not been implemented yet.
2021-01-20 15:05:32 +08:00
Harry Ho
f25e86e934
kc705: revive DRTIO satellite with updated syntax, update GTX
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* Multi-channel has not been implemented yet.
2021-01-20 11:25:38 +08:00
Harry Ho
cff7bcc122
Merge branch 'master' ( 43be383c86
) into k7-drtio
2020-12-31 13:30:46 +08:00
Harry Ho
dc7addf394
Revert "drtio: remove KC705/GTX support"
...
This reverts commit ebdbaaad32
.
2020-12-31 13:29:50 +08:00
Sebastien Bourdeauducq
ea95d91428
wrpll: separate collector reset
2020-11-09 17:57:13 +08:00
Sebastien Bourdeauducq
d185f1ac67
wrpll: fix mulshift (2)
2020-10-17 00:32:02 +08:00
Sebastien Bourdeauducq
3f076bf79b
wrpll: fix mulshift
2020-10-16 22:05:37 +08:00
Sebastien Bourdeauducq
db62cf2abe
wrpll: convert tests to self-checking unittests
2020-10-08 18:38:01 +08:00
Sebastien Bourdeauducq
07d43b6e5f
wrpll: babysit Vivado DSP retiming
...
Design now passes timing.
2020-10-08 17:51:27 +08:00
Sebastien Bourdeauducq
6248970ef8
wrpll: clean up matlab comparison test
2020-10-08 15:40:15 +08:00
hartytp
cd8c2ce713
wrpll: add test to compare collector+filter against Matlab simulation
2020-10-08 15:36:56 +08:00
hartytp
d780faf4ac
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
hartytp
7d7be6e711
wrpll.core: move collector into helper CD so we can get tags out while the filters are reset
2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq
3fa5d0b963
wrpll: clean up sign extension
2020-10-08 15:32:27 +08:00
hartytp
87911810d6
wrpll.core: add CSRs to monitor the collector outputs
2020-10-08 15:32:27 +08:00
hartytp
f2f942a8b4
wrpll.ddmtd: remove CSRs from DDMTD
...
We will gather then from the collector output so we can get all tags on the same cycle
2020-10-08 15:32:27 +08:00
hartytp
85bb641917
wrpll.ddmtd: fix first edge deglitcher
...
The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
2020-10-08 15:32:27 +08:00
hartytp
f3cd0fc675
wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit.
...
TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
2020-10-08 15:32:27 +08:00
hartytp
e5e648bde1
wrpll: add bit shift for collector helper output
2020-10-08 15:32:27 +08:00
hartytp
c9ae406ac6
wrpll: change the DDMTD helper frequency to match CERN, improve docs
2020-10-08 15:32:27 +08:00
hartytp
f6f6045f1a
wrpll.thls: fix make
2020-10-08 15:32:27 +08:00
hartytp
b44b870452
wrpll.filters: update to match Weida's MatLab simulations
2020-10-08 15:32:27 +08:00
hartytp
e9ab434fa7
wrpll.core: update for modified collector
2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq
17c952b8fb
wrpll: style
2020-10-08 15:32:27 +08:00
hartytp
ebb7ccbfd1
wrpll: document DDMTD collector and fix unwrapping
2020-10-08 15:32:27 +08:00
cw-mlabs
e4b16428f5
wrpll: fix run signal
2020-07-27 13:02:02 +08:00
cw-mlabs
8dd9a6d024
wrpll: fix scl signal
2020-07-27 12:59:32 +08:00
Sebastien Bourdeauducq
61d4614b61
sayma: fix/cleanup DRTIO-DAC sync interaction
2020-04-06 22:34:05 +08:00
Sebastien Bourdeauducq
dfa033eb87
wrpll: new collector from Weida/Tom
2020-01-24 10:31:52 +08:00
Sebastien Bourdeauducq
dee16edb78
wrpll: DDMTD sampler double latching
2020-01-22 19:16:26 +08:00
Sebastien Bourdeauducq
6c3e71a83a
wrpll: cleanup
2020-01-18 09:43:43 +08:00
Sebastien Bourdeauducq
344f8bd12a
wrpll: collector patch from Weida
2020-01-18 09:42:58 +08:00
Sebastien Bourdeauducq
50302d57c0
wrpll: more careful I2C timing
2020-01-14 20:03:46 +08:00
Sebastien Bourdeauducq
105dd60c78
wrpll: ADPLLProgrammer mini test bench and fixes
2020-01-14 16:52:25 +08:00
Sebastien Bourdeauducq
3242e9ec6c
wrpll: loop test
2020-01-13 22:31:57 +08:00
Sebastien Bourdeauducq
8ec0f2e717
wrpll: implement ADPLLProgrammer
2020-01-13 22:30:11 +08:00
Sebastien Bourdeauducq
d685619bcd
wrpll: collector code modifications from Weida
2020-01-13 20:42:41 +08:00
Sebastien Bourdeauducq
a666766f38
wrpll: add ADPLL offset registers
2019-12-30 22:19:42 +08:00
Sebastien Bourdeauducq
5c6e394928
ddmtd: add collector
2019-12-30 22:17:44 +08:00
Sebastien Bourdeauducq
f57f235dca
wrpll: new frequency meter
...
As per Mattermost discussion with Tom.
2019-12-30 19:47:57 +08:00
Sebastien Bourdeauducq
9e15ff7e6a
wrpll: improve DDMTD deglitcher
2019-12-30 16:56:06 +08:00
Sebastien Bourdeauducq
307a6ca140
gth_ultrascale: make OBUFDS_GTE3 work
...
https://www.xilinx.com/support/answers/67919.html
2019-12-09 18:13:22 +08:00
Sebastien Bourdeauducq
05e2e1899a
wrpll: update OBUFDS_GTE2 comment
...
Seems O can fan out simultaneously to transceiver and fabric.
Kasli is using ODIV2 for no particular reason.
2019-12-09 11:58:54 +08:00