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Commit Graph

7193 Commits

Author SHA1 Message Date
540bdae99c grabber: enable DIFF_TERM on inputs 2018-07-01 09:28:51 +08:00
0483b8d14c sayma_drtio: ditto 2018-06-28 17:03:32 +08:00
04d6ff45c8 kasli_sawgmaster: reset SAWGs
Most importantly this resets the phase accumulators.
2018-06-28 17:01:48 +08:00
729ce58f98 sayma: use GTP_CLK1 to clock DRTIO satellite transceiver
This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.

Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
2018-06-28 11:23:40 +08:00
a65721d649 sayma: put RTM clock tree into the siphaser loop
* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
2018-06-27 21:46:55 +08:00
d49716dfac satman: tune Sayma SYSREF phases 2018-06-27 18:09:35 +08:00
46c044099c hmc7043,satman: verify alignment of SYSREF slips 2018-06-27 17:36:13 +08:00
7dfd70c502 hmc7043: make margin_{minus,plus} consistent with ad9154 2018-06-27 17:35:26 +08:00
4bbdd43bdf hmc7043: do not freeze if SYSREF slip fails 2018-06-27 17:32:56 +08:00
a8a2ad68d3 runtime: tune Sayma SYSREF phases 2018-06-27 17:31:29 +08:00
apatura-iris
e9a1e10221 Update installing.rst
Added comment to clarify that ``artiq-main`` is the conda environment.
2018-06-27 08:18:50 +02:00
apatura-iris
5e5cdf0e67 Update installing.rst
The file 99-openocd.rules as downloaded from githubusercontent.com seems to be outdated and does now work on Ubuntu 16.04. The version that ships with OpenOCD has an additional ``TAG+="uaccess"`` in the rules file and works fine. Thus I suggest to use the file that is bundled with OpenOCD.
2018-06-27 08:18:50 +02:00
811882943b artiq_flash: RTM gateware is not required for master variant 2018-06-25 18:28:55 +08:00
c750de2955 sayma: add many-port pure DRTIO master 2018-06-25 18:21:22 +08:00
84b3d9ecc6 bootloader: also check firmware CRC in SDRAM (#1065) 2018-06-23 11:28:12 +08:00
68530fde07 sayma: generate 100MHz from Si5324 on standalone and master targets
* Allow switching between DRTIO satellite and standalone without
  touching the hardware.
* Allow operating standalone and master without an additional RF
  signal generator.
2018-06-23 10:44:38 +08:00
whitequark
b6dd9c8bb0 runtime: support builds without RTIO DMA.
Fixes #1079.
2018-06-23 00:56:21 +00:00
whitequark
12fde6d34b artiq_coremgmt: fix typo.
Fixes #1056.
2018-06-23 00:36:59 +00:00
51a5d8dff9 examples: add Kasli SAWG master 2018-06-22 18:57:49 +08:00
f87da95e57 jesd204: use jesd clock domain for sysref sampler
RTIO domain is still in reset during calibration.
2018-06-22 17:13:01 +08:00
76fc63bbf7 jesd204: use separate controls for reset and input buffer disable 2018-06-22 11:38:18 +08:00
d9955fee76 jesd204: make sure IOB FF is used to sample SYSREF at FPGA 2018-06-22 11:00:56 +08:00
60b22217ce sayma: set DRTIO master HMC830_REF to 100MHz 2018-06-22 10:10:09 +08:00
e6d1726754 sayma: add RTIO log to DRTIO master 2018-06-22 00:05:22 +08:00
83428961ad sayma: add SAWG and JESD to DRTIO master 2018-06-22 00:04:22 +08:00
c1db02a351 drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin
Precaution against HMC7043 noise issues.
2018-06-21 22:56:07 +08:00
8b3c12e6eb sayma: clock DRTIO master transceiver from HMC7043 2018-06-21 22:34:44 +08:00
de7d64d482 sayma: clock JESD204 from GTP CLK2
This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
2018-06-21 22:33:53 +08:00
b28ff587c5 sayma: add sysref sampler to DRTIO master 2018-06-21 22:28:34 +08:00
07bcdfd91e hmc7043: stricter check of FPGA SYSREF margin 2018-06-21 22:26:49 +08:00
e29536351d drtio: resync SYSREF when TSC is loaded 2018-06-21 17:00:32 +08:00
5a2a857a2f firmware: clean up SYSREF phase management 2018-06-21 16:23:41 +08:00
05e908a0fd hmc7043: align SYSREF with RTIO 2018-06-21 15:54:42 +08:00
9741654cad hmc7043: style 2018-06-21 15:54:42 +08:00
45e8263208 hmc7043: do not configure phases during initial init
They are determined later on.
2018-06-21 15:54:42 +08:00
whitequark
7cc3da4faf firmware: do not lose the ".dirty" suffix in build versions.
Fixes #1074.
2018-06-21 05:18:51 +00:00
whitequark
095ee28fd9 runtime: fix size values for bytes and bytearray RPCs.
Fixes #1076.
2018-06-21 00:51:56 +00:00
whitequark
9260cdb2e8 compiler: support conversion of list to bytearray and bytes.
Fixes #1077.
2018-06-21 00:40:45 +00:00
5a91f820fd examples: change Sayma sines frequency to 9MHz
Well within Red Pitaya bandwidth.
2018-06-20 22:40:07 +08:00
9288301543 examples: add DRTIO sines 2018-06-20 22:39:40 +08:00
28fb0fd754 sayma: add SYSREF sampler gateware 2018-06-20 17:48:35 +08:00
814d0583db hmc7043: improve smoothness of sysref phase control 2018-06-20 17:40:48 +08:00
9142a5ab8a rtio: expose coarse timestamp in RTIO and DRTIO satellite cores 2018-06-20 17:39:54 +08:00
5272c11704 typo 2018-06-20 17:05:20 +08:00
0c32d07e8b ad9154: new sysref scan
Print margins around the pre-defined fixed phase.
Also report error if margins are too small.

The fixed phase is also changed by this commit (the value 88 is
from before the new HMC7043 initialization code, and is probably wrong).
2018-06-20 00:15:58 +08:00
4803ca3799 examples/sayma_drtio: add SAWG channels 2018-06-19 23:50:26 +08:00
3d0e92aefd hmc7043: check that chip is disabled at startup 2018-06-19 23:49:17 +08:00
740e6863c3 hmc7043: add delay after releasing hardware reset 2018-06-19 23:48:48 +08:00
75b6cea52f sayma: add SAWG to DRTIO satellite 2018-06-19 19:12:10 +08:00
eb3259b847 firmware: reduce number of DAC initialization attempts
Faster startup when one DAC is broken.
2018-06-19 19:10:23 +08:00