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https://github.com/m-labs/artiq.git
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hmc7043: align SYSREF with RTIO
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9741654cad
commit
05e908a0fd
@ -770,6 +770,12 @@ pub fn init() {
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// set up clock chips before.
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jesd_unreset();
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// This needs to take place once before DAC SYSREF scan, as
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// the HMC7043 input clock (which defines slip resolution)
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// is 2x the DAC clock, so there are two possible phases from
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// the divider states. This deterministically selects one.
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hmc7043::sysref_rtio_align();
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for dacno in 0..csr::AD9154.len() {
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match init_dac(dacno as u8) {
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Ok(_) => (),
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@ -283,11 +283,12 @@ pub mod hmc7043 {
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let (enabled, divider, outcfg) = OUTPUT_CONFIG[channel];
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if enabled {
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// Only clock channels need to be high-performance
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if channel % 2 == 0 {
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// DCLK channel: enable high-performance mode
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write(channel_base, 0xd1);
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} else {
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write(channel_base, 0x51);
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// SYSREF channel: disable hi-perf mode, enable slip
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write(channel_base, 0x71);
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}
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} else {
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write(channel_base, 0x10);
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@ -336,6 +337,68 @@ pub mod hmc7043 {
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}
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}
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fn cfg_fpga_sysref(phase: u16) {
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let analog_delay = (phase % 17) as u8;
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let digital_delay = (phase / 17) as u8;
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spi_setup();
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write(0x0111, analog_delay);
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write(0x0112, digital_delay);
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}
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fn sysref_slip() {
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spi_setup();
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write(0x0002, 0x02);
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write(0x0002, 0x00);
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}
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fn sysref_sample() -> bool {
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unsafe { csr::sysref_sampler::sample_result_read() == 1 }
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}
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pub fn sysref_rtio_align() {
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info!("aligning SYSREF with RTIO...");
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let phase_offset = 44;
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let mut slips0 = 0;
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let mut slips1 = 0;
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// meet setup/hold (assuming FPGA timing margins are OK)
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cfg_fpga_sysref(phase_offset);
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// if we are already in the 1 zone, get out of it
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while sysref_sample() {
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sysref_slip();
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slips0 += 1;
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}
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// get to the edge of the 0->1 transition (our final setpoint)
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while !sysref_sample() {
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sysref_slip();
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slips1 += 1;
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}
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info!(" ...done ({}/{} slips), verifying timing margin", slips0, slips1);
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let mut margin = None;
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for d in 0..phase_offset {
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cfg_fpga_sysref(phase_offset - d);
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if !sysref_sample() {
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margin = Some(d);
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break;
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}
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}
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// meet setup/hold
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cfg_fpga_sysref(phase_offset);
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if margin.is_some() {
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let margin = margin.unwrap();
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info!(" margin at FPGA: {}", margin);
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if margin < 10 {
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error!("SYSREF margin at FPGA is too small");
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}
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} else {
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error!("unable to determine SYSREF margin at FPGA");
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}
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}
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}
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pub fn init() -> Result<(), &'static str> {
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