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https://github.com/m-labs/artiq.git
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firmware: clean up SYSREF phase management
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05e908a0fd
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@ -703,11 +703,11 @@ fn dac_sysref_scan(dacno: u8, center_phase: u16) {
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info!("AD9154-{} SYSREF scan...", dacno);
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hmc7043::cfg_dac_sysref(dacno, center_phase);
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hmc7043::sysref_offset_dac(dacno, center_phase);
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clock::spin_us(10000);
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let mut sync_error_last = dac_get_sync_error(dacno);
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for d in 0..128 {
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hmc7043::cfg_dac_sysref(dacno, center_phase - d);
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hmc7043::sysref_offset_dac(dacno, center_phase - d);
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clock::spin_us(10000);
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let sync_error = dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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@ -717,11 +717,11 @@ fn dac_sysref_scan(dacno: u8, center_phase: u16) {
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}
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}
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hmc7043::cfg_dac_sysref(dacno, center_phase);
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hmc7043::sysref_offset_dac(dacno, center_phase);
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clock::spin_us(10000);
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sync_error_last = dac_get_sync_error(dacno);
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for d in 0..128 {
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hmc7043::cfg_dac_sysref(dacno, center_phase + d);
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hmc7043::sysref_offset_dac(dacno, center_phase + d);
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clock::spin_us(10000);
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let sync_error = dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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@ -743,12 +743,7 @@ fn dac_sysref_scan(dacno: u8, center_phase: u16) {
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}
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}
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fn dac_sysref_cfg(dacno: u8, phase: u16) {
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info!("AD9154-{} setting SYSREF phase to {}", dacno, phase);
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hmc7043::cfg_dac_sysref(dacno, phase);
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}
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fn init_dac(dacno: u8) -> Result<(), &'static str> {
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fn init_dac(dacno: u8, sysref_phase: u16) -> Result<(), &'static str> {
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let dacno = dacno as u8;
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// Reset the DAC, detect and configure it
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dac_reset(dacno);
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@ -757,15 +752,14 @@ fn init_dac(dacno: u8) -> Result<(), &'static str> {
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// Run the PRBS, STPL and SYSREF scan tests
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dac_prbs(dacno)?;
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dac_stpl(dacno, 4, 2)?;
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let sysref_phase = 61;
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dac_sysref_scan(dacno, sysref_phase);
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// Set SYSREF phase and reconfigure the DAC
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dac_sysref_cfg(dacno, sysref_phase);
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hmc7043::sysref_offset_dac(dacno, sysref_phase);
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dac_cfg_retry(dacno)?;
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Ok(())
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}
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pub fn init() {
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pub fn init(sysref_phase_fpga: u16, sysref_phase_dac: u16) {
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// Release the JESD clock domain reset late, as we need to
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// set up clock chips before.
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jesd_unreset();
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@ -774,10 +768,12 @@ pub fn init() {
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// the HMC7043 input clock (which defines slip resolution)
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// is 2x the DAC clock, so there are two possible phases from
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// the divider states. This deterministically selects one.
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hmc7043::sysref_rtio_align();
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hmc7043::sysref_rtio_align(sysref_phase_fpga);
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for dacno in 0..csr::AD9154.len() {
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match init_dac(dacno as u8) {
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// We assume DCLK and SYSREF traces are matched on the PCB
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// (they are on Sayma) so only one phase is needed.
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match init_dac(dacno as u8, sysref_phase_dac) {
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Ok(_) => (),
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Err(e) => error!("failed to initialize AD9154-{}: {}", dacno, e)
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}
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@ -318,13 +318,13 @@ pub mod hmc7043 {
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info!(" ...done");
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}
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pub fn cfg_dac_sysref(dacno: u8, phase: u16) {
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pub fn sysref_offset_dac(dacno: u8, phase_offset: u16) {
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/* Analog delay resolution: 25ps
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* Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
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* 16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
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*/
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let analog_delay = (phase % 17) as u8;
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let digital_delay = (phase / 17) as u8;
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let analog_delay = (phase_offset % 17) as u8;
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let digital_delay = (phase_offset / 17) as u8;
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spi_setup();
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if dacno == 0 {
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write(0x00d5, analog_delay);
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@ -337,9 +337,9 @@ pub mod hmc7043 {
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}
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}
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fn cfg_fpga_sysref(phase: u16) {
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let analog_delay = (phase % 17) as u8;
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let digital_delay = (phase / 17) as u8;
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fn sysref_offset_fpga(phase_offset: u16) {
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let analog_delay = (phase_offset % 17) as u8;
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let digital_delay = (phase_offset / 17) as u8;
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spi_setup();
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write(0x0111, analog_delay);
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write(0x0112, digital_delay);
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@ -355,15 +355,13 @@ pub mod hmc7043 {
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unsafe { csr::sysref_sampler::sample_result_read() == 1 }
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}
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pub fn sysref_rtio_align() {
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pub fn sysref_rtio_align(phase_offset: u16) {
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info!("aligning SYSREF with RTIO...");
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let phase_offset = 44;
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let mut slips0 = 0;
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let mut slips1 = 0;
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// meet setup/hold (assuming FPGA timing margins are OK)
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cfg_fpga_sysref(phase_offset);
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sysref_offset_fpga(phase_offset);
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// if we are already in the 1 zone, get out of it
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while sysref_sample() {
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sysref_slip();
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@ -374,12 +372,11 @@ pub mod hmc7043 {
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sysref_slip();
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slips1 += 1;
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}
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info!(" ...done ({}/{} slips), verifying timing margin", slips0, slips1);
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let mut margin = None;
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for d in 0..phase_offset {
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cfg_fpga_sysref(phase_offset - d);
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sysref_offset_fpga(phase_offset - d);
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if !sysref_sample() {
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margin = Some(d);
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break;
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@ -387,7 +384,7 @@ pub mod hmc7043 {
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}
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// meet setup/hold
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cfg_fpga_sysref(phase_offset);
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sysref_offset_fpga(phase_offset);
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if margin.is_some() {
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let margin = margin.unwrap();
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@ -109,7 +109,7 @@ fn startup() {
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/* must be the first SPI init because of HMC830 SPI mode selection */
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board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
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#[cfg(has_ad9154)]
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board_artiq::ad9154::init();
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board_artiq::ad9154::init(44, 61);
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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@ -262,7 +262,7 @@ pub extern fn main() -> i32 {
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/* must be the first SPI init because of HMC830 SPI mode selection */
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hmc830_7043::init().expect("cannot initialize HMC830/7043");
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#[cfg(has_ad9154)]
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board_artiq::ad9154::init();
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board_artiq::ad9154::init(32, 61);
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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