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hmc7043: improve smoothness of sysref phase control
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@ -757,7 +757,7 @@ fn init_dac(dacno: u8) -> Result<(), &'static str> {
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// Run the PRBS, STPL and SYSREF scan tests
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dac_prbs(dacno)?;
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dac_stpl(dacno, 4, 2)?;
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let sysref_phase = 58;
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let sysref_phase = 61;
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dac_sysref_scan(dacno, sysref_phase);
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// Set SYSREF phase and reconfigure the DAC
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dac_sysref_cfg(dacno, sysref_phase);
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@ -318,12 +318,14 @@ pub mod hmc7043 {
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* Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
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* 16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
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*/
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let analog_delay = (phase % 17) as u8;
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let digital_delay = (phase / 17) as u8;
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if dacno == 0 {
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write(0x00d5, (phase & 0xf) as u8);
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write(0x00d6, ((phase >> 4) & 0x1f) as u8);
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write(0x00d5, analog_delay);
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write(0x00d6, digital_delay);
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} else if dacno == 1 {
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write(0x00e9, (phase & 0xf) as u8);
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write(0x00ea, ((phase >> 4) & 0x1f) as u8);
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write(0x00e9, analog_delay);
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write(0x00ea, digital_delay);
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} else {
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unimplemented!();
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}
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