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https://github.com/m-labs/artiq.git
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ad9154: new sysref scan
Print margins around the pre-defined fixed phase. Also report error if margins are too small. The fixed phase is also changed by this commit (the value 88 is from before the new HMC7043 initialization code, and is probably wrong).
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@ -689,36 +689,58 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> {
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}
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}
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fn dac_sysref_scan(dacno: u8) {
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let mut sync_error_last = 0;
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let mut phase_min = None;
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let mut phase_max = None;
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fn dac_get_sync_error(dacno: u8) -> u16 {
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spi_setup(dacno);
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let sync_error = ((read(ad9154_reg::SYNC_CURRERR_L) as u16) |
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((read(ad9154_reg::SYNC_CURRERR_H) as u16) << 8))
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& 0x1ff;
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sync_error
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}
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info!("AD9154-{} SYSREF scan:", dacno);
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for phase in 0..512 {
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hmc7043::cfg_dac_sysref(dacno, phase);
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fn dac_sysref_scan(dacno: u8, center_phase: u16) {
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let mut margin_minus = None;
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let mut margin_plus = None;
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info!("AD9154-{} SYSREF scan...", dacno);
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hmc7043::cfg_dac_sysref(dacno, center_phase);
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clock::spin_us(10000);
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let mut sync_error_last = dac_get_sync_error(dacno);
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for d in 0..128 {
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hmc7043::cfg_dac_sysref(dacno, center_phase - d);
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clock::spin_us(10000);
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spi_setup(dacno);
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let sync_error = ((read(ad9154_reg::SYNC_CURRERR_L) as u16) |
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((read(ad9154_reg::SYNC_CURRERR_H) as u16) << 8))
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& 0x1ff;
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let sync_error = dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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info!(" phase: {}, sync error: {}", phase, sync_error);
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info!(" sync error-: {} -> {}", sync_error_last, sync_error);
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margin_minus = Some(d);
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break;
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}
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if sync_error != 0 {
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if phase_min.is_some() {
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if sync_error != sync_error_last {
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phase_max = Some(phase - 1);
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break;
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}
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} else {
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phase_min = Some(phase);
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}
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}
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sync_error_last = sync_error;
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}
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info!(" phase min: {:?}, phase max: {:?}", phase_min, phase_max);
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hmc7043::cfg_dac_sysref(dacno, center_phase);
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clock::spin_us(10000);
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sync_error_last = dac_get_sync_error(dacno);
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for d in 0..128 {
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hmc7043::cfg_dac_sysref(dacno, center_phase + d);
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clock::spin_us(10000);
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let sync_error = dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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info!(" sync error+: {} -> {}", sync_error_last, sync_error);
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margin_plus = Some(d);
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break;
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}
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}
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if margin_minus.is_some() && margin_plus.is_some() {
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let margin_minus = margin_minus.unwrap();
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let margin_plus = margin_plus.unwrap();
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info!(" margins: -{} +{}", margin_minus, margin_plus);
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if margin_minus < 10 || margin_plus < 10 {
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error!("SYSREF margins are too small");
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}
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} else {
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error!("Unable to determine SYSREF margins");
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}
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}
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fn dac_sysref_cfg(dacno: u8, phase: u16) {
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@ -735,9 +757,10 @@ fn init_dac(dacno: u8) -> Result<(), &'static str> {
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// Run the PRBS, STPL and SYSREF scan tests
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dac_prbs(dacno)?;
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dac_stpl(dacno, 4, 2)?;
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dac_sysref_scan(dacno);
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let sysref_phase = 58;
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dac_sysref_scan(dacno, sysref_phase);
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// Set SYSREF phase and reconfigure the DAC
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dac_sysref_cfg(dacno, 88);
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dac_sysref_cfg(dacno, sysref_phase);
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dac_cfg_retry(dacno)?;
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Ok(())
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}
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