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satman: tune Sayma SYSREF phases
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@ -250,9 +250,9 @@ fn drtio_link_rx_up() -> bool {
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const SIPHASER_PHASE: u16 = 32;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_FPGA: u16 = 32;
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const SYSREF_PHASE_FPGA: u16 = 53;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_DAC: u16 = 61;
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const SYSREF_PHASE_DAC: u16 = 64;
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#[no_mangle]
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pub extern fn main() -> i32 {
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