Sebastien Bourdeauducq
c22482787e
sayma_amc: fix syntax
2021-02-17 17:45:54 +08:00
Sebastien Bourdeauducq
6861d3ab33
remove WRPLL
2021-02-17 16:09:51 +08:00
Sebastien Bourdeauducq
e54dd08821
metlino,sayma: adapt to new EEM API
...
This also enables 4X SERDES TTLs.
2021-02-10 15:32:10 +08:00
Astro
461199b903
kasli_generic: warn if min_artiq_version is not met
2021-02-10 15:26:15 +08:00
Sebastien Bourdeauducq
f7a33a1f99
gateware: make 7-series EEM handling functions shareable
2021-02-07 14:34:26 +08:00
Sebastien Bourdeauducq
c675488a99
reorganize JSON schema files
2021-01-16 10:43:14 +08:00
Astro
c6807f4594
kasli_generic: validate description against schema, use defaults from schema
2021-01-16 10:35:23 +08:00
Astro
45b5cfce05
gateware: add a kasli_generic.schema.json
2021-01-16 10:35:23 +08:00
Harry Ho
43ecb3fea6
sayma: add comments about CPLL line rate on KU GTH
2020-12-19 17:05:20 +08:00
Sebastien Bourdeauducq
ccdc741e73
sayma_amc: fix --sfp argument
2020-12-07 18:02:36 +08:00
Robert Jördens
a9dd0a268c
Merge pull request #1533 from m-labs/phaser
...
Phaser
2020-10-19 09:30:12 +02:00
Sebastien Bourdeauducq
7dfb4af682
kasli2: work around vivado clock constraint problem
2020-10-08 16:31:39 +08:00
Sebastien Bourdeauducq
96a5df0dc6
kasli2: add false path constraint for wrpll helper clock
2020-10-08 16:19:44 +08:00
Robert Jördens
50b4eb4840
Merge branch 'master' into phaser
...
* master: (26 commits)
fastino: documentation and eem pass-through
kasli2: forward sma_clkin to si5324
test: relax test_dma_playback_time on Zynq
rpc: fixed _write_bool
fastino: document/cleanup
build_soc: remove assertion that was used for test runs
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516 )
Revert "test: temporarily disable test_async_throughput"
build_soc: rename identifier_str to gateware_identifier_str
test: relax loopback gate timing
test: temporarily disable test_async_throughput
test: relax test_pulse_rate on Zynq
test: skip NonexistentI2CBus if I2C is not supported
build_soc: override identifier_str only for gateware
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
sayma_amc: add support for 4x DIO output channels via FMC
fmcdio_vhdci_eem: fix pin naming
build_soc: add identifier_str override option
RPC: optimization by caching
test: improved test_performance
...
2020-09-22 16:02:25 +00:00
Robert Jördens
c55f2222dc
fastino: documentation and eem pass-through
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* Repeat information about matching log2_width a few times
in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
Sebastien Bourdeauducq
29c940f4e3
kasli2: forward sma_clkin to si5324
2020-09-17 16:53:43 +08:00
Astro
002a71dd8d
build_soc: rename identifier_str to gateware_identifier_str
2020-09-02 00:00:57 +08:00
Harry Ho
dfbf3311cb
sayma_amc: add support for 4x DIO output channels via FMC
2020-08-31 16:21:45 +08:00
Astro
45ae6202c0
build_soc: add identifier_str override option
...
Signed-off-by: Stephan Maka <stephan@spaceboyz.net>
2020-08-31 11:48:58 +08:00
Robert Jördens
aa0154d8e2
phaser: initial
2020-08-22 11:56:23 +00:00
Sebastien Bourdeauducq
901be75ba4
sayma_rtm: fix Si5324 reset
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Closes #1483
2020-07-11 09:51:01 +08:00
Sebastien Bourdeauducq
2d1f1fff7f
kasli_generic: do not attempt to use SFP LED for RTIO on 2.0+
2020-07-08 18:14:44 +08:00
Sebastien Bourdeauducq
cb76f9da89
metlino: fix CSR collisions
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Closes #1425
2020-05-29 15:59:44 +08:00
Sebastien Bourdeauducq
bd9eec15c0
metlino: increase number of DRTIO links
...
Seems OK with Vivado 2019.2.
2020-05-29 15:59:16 +08:00
Sebastien Bourdeauducq
d8b5bcf019
sayma_amc: support uTCA backplane for DRTIO
2020-05-29 14:58:49 +08:00
Sebastien Bourdeauducq
8b939b7cb3
sayma_amc: remove Master (obsoleted by Metlino)
2020-05-29 14:40:49 +08:00
Sebastien Bourdeauducq
4e9a529e5a
kasli: integrate WRPLL
2020-05-07 21:34:02 +08:00
Sebastien Bourdeauducq
60e5f1c18e
kasli: DRTIO support for Kasli 2
2020-05-07 20:09:43 +08:00
Sebastien Bourdeauducq
1f2182d4c7
kasli: default to hardware v2
2020-05-07 19:15:03 +08:00
Sebastien Bourdeauducq
b83afedf43
kasli: light up ERROR LED on panic
2020-05-07 19:06:10 +08:00
Sebastien Bourdeauducq
7e400a78f4
kasli: compile tester for hw 2.0 by default
2020-04-28 16:07:56 +08:00
Sebastien Bourdeauducq
d19f28fa84
kasli: v2 clocking WIP, remove SFP LEDs from RTIO
2020-04-23 23:02:18 +08:00
Sebastien Bourdeauducq
ec7b2bea12
sayma: round FTW like Urukul in JDCGSyncDDS
2020-04-08 15:00:33 +08:00
Sebastien Bourdeauducq
0f4be22274
sayma: add simple sychronized DDS for testing
2020-04-08 14:13:54 +08:00
Sebastien Bourdeauducq
ffd3172e02
sayma: move SYSREF DDMTD to RTM ( #795 )
2020-04-06 00:01:28 +08:00
Sebastien Bourdeauducq
6d26def3ce
sayma: drive filtered_clk_sel on master variant
2020-02-06 22:28:49 +08:00
Sebastien Bourdeauducq
c7de1f2e6b
metlino: drive clock muxes
2020-02-05 00:06:34 +08:00
Robert Jördens
248230a89e
fastino: style
2020-01-20 13:25:00 +01:00
Robert Jördens
2c4e5bfee4
fastino: add [WIP]
2020-01-20 13:25:00 +01:00
Robert Jördens
01a6e77d89
mirny: add
...
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1 )
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written
Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
Sebastien Bourdeauducq
6c948c7726
sayma: RF switch control is active-low on Basemod, invert
2020-01-16 08:59:52 +08:00
Sebastien Bourdeauducq
b7f1623197
sayma_rtm: connect attenuator shift registers in series
2019-12-20 18:58:31 +08:00
Sebastien Bourdeauducq
1c9cbe6285
sayma_rtm: add basemod attenuators on RTIO
2019-12-20 15:25:55 +08:00
Sebastien Bourdeauducq
6ee15fbcae
sayma_rtm: basemod RF switches
2019-12-18 10:33:29 +08:00
Sebastien Bourdeauducq
52112d54f9
kasli_generic: expose peripheral_processors dictionary. Closes #1403
2019-12-10 10:30:06 +08:00
Sebastien Bourdeauducq
150a02117c
sayma_rtm: drive clk_src_ext_sel
2019-12-09 19:47:50 +08:00
Sebastien Bourdeauducq
2b5213b013
wrpll: constrain clocks
2019-12-09 12:26:44 +08:00
Sebastien Bourdeauducq
46a776d06e
sayma: introduce WRPLL on RTM
2019-12-08 15:30:00 +08:00
Sebastien Bourdeauducq
883310d83e
sayma_rtm: si5324 -> cdrclkc
2019-12-08 14:26:05 +08:00
Sebastien Bourdeauducq
57a5bea43a
sayma_rtm: support setting RTIO frequency
2019-12-08 11:45:31 +08:00