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259 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 6861d3ab33 remove WRPLL 2021-02-17 16:09:51 +08:00
Sebastien Bourdeauducq ea95d91428 wrpll: separate collector reset 2020-11-09 17:57:13 +08:00
hartytp e6ff2ddc32 wrpll: add more diagnostics in firmware and adapt to recent gateware changes 2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq 4e9a529e5a kasli: integrate WRPLL 2020-05-07 21:34:02 +08:00
Sebastien Bourdeauducq ffd3172e02 sayma: move SYSREF DDMTD to RTM (#795) 2020-04-06 00:01:28 +08:00
Sebastien Bourdeauducq 52ec849008 sayma: fix sysref_delay_dac 2020-02-05 19:04:01 +08:00
Sebastien Bourdeauducq bf9f4e380a si5324: program I2C mux on Metlino 2020-02-03 18:07:59 +08:00
Sebastien Bourdeauducq ec03767dcf sayma: improve DAC status report 2020-01-20 18:22:06 +08:00
Sebastien Bourdeauducq 3242e9ec6c wrpll: loop test 2020-01-13 22:31:57 +08:00
Sebastien Bourdeauducq d5895b8999 wrpll: adpll -> set_adpll 2020-01-13 20:46:36 +08:00
Sebastien Bourdeauducq e7ef23d30c wrpll: use CONFIG_CLOCK_FREQUENCY and rtio_frequency in trim_dcxos 2020-01-13 20:44:15 +08:00
Sebastien Bourdeauducq ea3bce6fe3 wrpll: wait for settling time after setting ADPLL 2020-01-13 20:43:34 +08:00
Sebastien Bourdeauducq e87d864063 wrpll: print ADPLL offsets 2020-01-13 19:32:30 +08:00
Sebastien Bourdeauducq 8edbc33d0e wrpll: calculate initial ADPLL offsets 2020-01-13 19:29:10 +08:00
Sebastien Bourdeauducq 3f32d78c0e wrpll: simple ADPLL test 2019-12-31 12:12:29 +08:00
Sebastien Bourdeauducq bb04b082a7 wrpll: clarify comment 2019-12-31 12:12:29 +08:00
Sebastien Bourdeauducq 642a305c6a wrpll: remove unnecessary delay 
Counting now happens in the sys domain with no CDC between counter and CPU.
 2019-12-30 20:01:06 +08:00
Sebastien Bourdeauducq f57f235dca wrpll: new frequency meter 
As per Mattermost discussion with Tom.
 2019-12-30 19:47:57 +08:00
Sebastien Bourdeauducq c5137eeb62 firmware: remove legacy hmc542 code 2019-12-20 15:25:55 +08:00
Sebastien Bourdeauducq 6f52540569 wrpll: fix previous commit 2019-12-09 20:13:55 +08:00
Sebastien Bourdeauducq 13486f3acf wrpll: swap helper/main si549 frequencies 2019-12-09 19:49:34 +08:00
Sebastien Bourdeauducq 4919fb8765 wrpll: print DDMTD helper tags 2019-12-09 17:39:22 +08:00
Sebastien Bourdeauducq 0d4eccc1a5 wrpll: improve debug output 2019-12-09 17:23:09 +08:00
Sebastien Bourdeauducq f633c62e8d wrpll: speed up si549 i2c access 2019-12-09 17:22:58 +08:00
Sebastien Bourdeauducq 14e09582b6 wrpll: work around si549 not working when lsdiv=2 2019-12-09 16:20:08 +08:00
Sebastien Bourdeauducq 439576f59d wrpll: fix Si549 initialization delays 2019-12-09 16:13:57 +08:00
Sebastien Bourdeauducq 0499f83580 wrpll: helper clock sanity check 2019-12-08 23:46:33 +08:00
Paweł Kulik 14e250c78f Enabled internal pullup for CML SYSREF outputs, otherwise there is no signal on them. 
Signed-off-by: Paweł Kulik <pawel.kulik@creotech.pl>
 2019-12-07 09:30:24 +08:00
Sebastien Bourdeauducq eb271f383b wrpll: add DDMTD cores 2019-11-28 22:03:50 +08:00
Sebastien Bourdeauducq 39d5ca11f4 si549: increase I2C frequency 2019-11-28 22:03:26 +08:00
Sebastien Bourdeauducq 87894102e5 si549: use recommended i2c read sequence 2019-11-28 17:49:02 +08:00
Sebastien Bourdeauducq 354d82cfe3 wrpll: drive helper clock domain 2019-11-28 17:40:00 +08:00
Sebastien Bourdeauducq 68cab5be8c si549: cleanups 2019-11-28 16:36:59 +08:00
Sebastien Bourdeauducq bcd2383c9d wrpll: si549 initialization 2019-11-27 22:58:08 +08:00
Sebastien Bourdeauducq 4832bfb08c wrpll: i2c functions, select_recovered_clock placeholder 2019-11-27 21:21:00 +08:00
Sebastien Bourdeauducq a78e493b72 firmware: load slave FPGA in bootloader 2019-10-31 12:42:40 +08:00
Sebastien Bourdeauducq 389a8f587a slave_fpga: modularize 2019-10-31 11:50:53 +08:00
Sebastien Bourdeauducq f2f7170d20 hmc7043: use recommend I/O standards 
https://github.com/sinara-hw/Sayma_RTM/issues/116#issuecomment-544187952
 2019-10-21 22:56:10 +08:00
Sebastien Bourdeauducq 8f76a3218e firmware: move i2c to libboard_misoc, enable IPv6 in bootloader, share network settings 2019-10-21 12:58:52 +08:00
Sebastien Bourdeauducq 05e8f24c24 sayma2: JESD204 synchronization 2019-10-18 23:28:47 +08:00
Sebastien Bourdeauducq 4df2c5d1fb sayma: prepare for SYSREF align 
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
 2019-10-08 12:30:47 +08:00
Sebastien Bourdeauducq 4b3baf4825 firmware: run PRBS and STPL JESD204 tests 2019-10-08 00:10:36 +08:00
Sebastien Bourdeauducq 90e3b83e80 hmc7043: turn on AMC_FPGA_SYSREF1 
Florent's JESD core won't work at all without.
 2019-10-06 22:49:00 +08:00
Sebastien Bourdeauducq 1bc7743e03 sayma: fix hmc7043 output settings for v2 hardware 2019-10-06 21:50:29 +08:00
Sebastien Bourdeauducq a421820a32 sayma: initialize DACs over DRTIO 2019-10-06 21:42:45 +08:00
Sebastien Bourdeauducq f62dc7e1d4 sayma: refactor JESD DAC channel groups 2019-10-06 20:15:09 +08:00
Sebastien Bourdeauducq c4c884b8ce ad9154: simplify, focus on AD9154 config and do not include JESD 2019-10-06 20:07:02 +08:00
Sebastien Bourdeauducq ad63908aff hmc830_7043: enable_fpga_ibuf -> unmute 2019-10-06 18:13:59 +08:00
Sebastien Bourdeauducq 5ad65b9d30 hmc830_7043: remove clock_mux 2019-10-06 18:13:27 +08:00
Sebastien Bourdeauducq e9b81f6e33 remove serwb 
DRTIO is a better solution
 2019-10-06 18:10:23 +08:00