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https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
sayma: initialize DACs over DRTIO
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f8e4cc37d0
commit
a421820a32
@ -350,11 +350,11 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
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0x1*ad9154_reg::LINK_EN | 0*ad9154_reg::LINK_PAGE |
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0*ad9154_reg::LINK_MODE | 0*ad9154_reg::CHECKSUM_MODE);
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info!(" ...done");
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status(dacno);
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Ok(())
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}
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#[allow(dead_code)]
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fn status(dacno: u8) {
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pub fn status(dacno: u8) {
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spi_setup(dacno);
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info!("SERDES_PLL_LOCK: {}",
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(read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB));
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@ -2,35 +2,35 @@ use board_misoc::csr;
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pub fn jesd_reset(reset: bool) {
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unsafe {
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csr::jesd_crg::jreset_write(if reset {1} else {0});
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csr::jesd_crg::jreset_write(if reset {1} else {0});
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}
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}
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fn jesd_enable(dacno: u8, en: bool) {
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pub fn jesd_enable(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
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}
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}
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fn jesd_ready(dacno: u8) -> bool {
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pub fn jesd_ready(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
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}
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}
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fn jesd_prbs(dacno: u8, en: bool) {
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pub fn jesd_prbs(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
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}
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}
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fn jesd_stpl(dacno: u8, en: bool) {
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pub fn jesd_stpl(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
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}
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}
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fn jesd_jsync(dacno: u8) -> bool {
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pub fn jesd_jsync(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
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}
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@ -53,6 +53,9 @@ pub enum Packet {
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SpiReadRequest { destination: u8, busno: u8 },
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SpiReadReply { succeeded: bool, data: u32 },
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SpiBasicReply { succeeded: bool },
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JdacSetupRequest { destination: u8, dacno: u8 },
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JdacBasicReply { succeeded: bool },
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}
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impl Packet {
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@ -178,6 +181,14 @@ impl Packet {
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succeeded: reader.read_bool()?
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},
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0xa0 => Packet::JdacSetupRequest {
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destination: reader.read_u8()?,
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dacno: reader.read_u8()?,
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},
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0xa1 => Packet::JdacBasicReply {
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succeeded: reader.read_bool()?
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},
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ty => return Err(Error::UnknownPacket(ty))
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})
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}
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@ -329,6 +340,16 @@ impl Packet {
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writer.write_u8(0x95)?;
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writer.write_bool(succeeded)?;
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},
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Packet::JdacSetupRequest { destination, dacno } => {
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writer.write_u8(0xa0)?;
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writer.write_u8(destination)?;
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writer.write_u8(dacno)?;
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}
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Packet::JdacBasicReply { succeeded } => {
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writer.write_u8(0xa1)?;
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writer.write_bool(succeeded)?;
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},
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}
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Ok(())
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}
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@ -288,6 +288,22 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
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}
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}
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drtioaux::Packet::JdacSetupRequest { destination: _destination, dacno: _dacno } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet);
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#[cfg(has_ad9154)]
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let succeeded = {
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#[cfg(rtio_frequency = "125.0")]
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const LINERATE: u64 = 5_000_000_000;
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#[cfg(rtio_frequency = "150.0")]
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const LINERATE: u64 = 6_000_000_000;
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board_artiq::ad9154::setup(_dacno, LINERATE).is_ok()
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};
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#[cfg(not(has_ad9154))]
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let succeeded = false;
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drtioaux::send(0,
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&drtioaux::Packet::JdacBasicReply { succeeded: succeeded })
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}
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_ => {
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warn!("received unexpected aux packet");
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Ok(())
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@ -400,6 +416,32 @@ const SI5324_SETTINGS: si5324::FrequencySettings
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crystal_ref: true
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};
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#[cfg(has_jdcg)]
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fn init_jdcgs() {
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for dacno in 0..csr::JDCG.len() {
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let dacno = dacno as u8;
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info!("DAC-{} initializing...", dacno);
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board_artiq::jdcg::jesd_enable(dacno, false);
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board_artiq::jdcg::jesd_prbs(dacno, false);
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board_artiq::jdcg::jesd_stpl(dacno, false);
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clock::spin_us(10000);
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board_artiq::jdcg::jesd_enable(dacno, true);
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if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacSetupRequest {
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destination: 0,
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dacno: dacno
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}) {
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error!("aux packet error ({})", e);
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}
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match drtioaux::recv_timeout(1, Some(1000)) {
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Ok(drtioaux::Packet::JdacBasicReply { succeeded }) =>
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if !succeeded { error!("DAC-{} initialization failed", dacno); },
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Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
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Err(e) => error!("aux packet error ({})", e),
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}
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info!(" ...done");
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}
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}
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#[no_mangle]
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pub extern fn main() -> i32 {
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clock::init();
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@ -473,19 +515,31 @@ pub extern fn main() -> i32 {
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* Si5324 is locked to the recovered clock.
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*/
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board_artiq::jdcg::jesd_reset(false);
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// TODO: board_artiq::ad9154::init();
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if repeaters[0].is_up() {
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init_jdcgs();
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}
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}
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drtioaux::reset(0);
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drtiosat_reset(false);
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drtiosat_reset_phy(false);
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#[cfg(has_jdcg)]
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let mut rep0_was_up = repeaters[0].is_up();
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while drtiosat_link_rx_up() {
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drtiosat_process_errors();
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process_aux_packets(&mut repeaters, &mut routing_table, &mut rank);
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for mut rep in repeaters.iter_mut() {
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rep.service(&routing_table, rank);
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}
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#[cfg(has_jdcg)]
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{
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let rep0_is_up = repeaters[0].is_up();
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if rep0_is_up && !rep0_was_up {
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init_jdcgs();
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}
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rep0_was_up = rep0_is_up;
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}
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hardware_tick(&mut hardware_tick_ts);
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if drtiosat_tsc_loaded() {
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info!("TSC loaded from uplink");
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@ -43,6 +43,10 @@ impl Repeater {
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}
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}
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pub fn is_up(&self) -> bool {
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self.state == RepeaterState::Up
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}
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pub fn service(&mut self, routing_table: &drtio_routing::RoutingTable, rank: u8) {
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self.process_local_errors();
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