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artiq
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wrpll: remove unnecessary delay 

Counting now happens in the sys domain with no CDC between counter and CPU.
pull/1405/head
Sebastien Bourdeauducq 2019-12-30 20:01:06 +08:00
parent f57f235dca
commit 642a305c6a
1 changed files with 0 additions and 1 deletions
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artiq/firmware/libboard_artiq/wrpll.rs
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@ -269,7 +269,6 @@ fn get_frequencies() -> (u32, u32, u32) {
csr::wrpll::frequency_counter_update_en_write(1);
clock::spin_us(200_000); // wait for at least one update
csr::wrpll::frequency_counter_update_en_write(0);
clock::spin_us(1);
let helper = csr::wrpll::frequency_counter_counter_helper_read();
let main = csr::wrpll::frequency_counter_counter_rtio_read();
let cdr = csr::wrpll::frequency_counter_counter_rtio_rx0_read();