wrpll: wait for settling time after setting ADPLL

2020-01-13 20:43:34 +08:00 · 2020-01-13 20:43:34 +08:00 · ea3bce6fe3
parent d685619bcd
commit ea3bce6fe3
1 changed files with 1 additions and 0 deletions
--- a/artiq/firmware/libboard_artiq/wrpll.rs
+++ b/artiq/firmware/libboard_artiq/wrpll.rs
@ -267,6 +267,7 @@ mod si549 {
        write(dcxo, 231, adpll as u8)?;
        write(dcxo, 232, (adpll >> 8) as u8)?;
        write(dcxo, 233, (adpll >> 16) as u8)?;
+        clock::spin_us(100);
        Ok(())
    }
 }