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wrpll: wait for settling time after setting ADPLL

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Sebastien Bourdeauducq 2020-01-13 20:43:34 +08:00
parent d685619bcd
commit ea3bce6fe3
1 changed files with 1 additions and 0 deletions
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artiq/firmware/libboard_artiq/wrpll.rs
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@ -267,6 +267,7 @@ mod si549 {
write(dcxo, 231, adpll as u8)?;
write(dcxo, 232, (adpll >> 8) as u8)?;
write(dcxo, 233, (adpll >> 16) as u8)?;
clock::spin_us(100);
Ok(())
}
}