52112d54f9
kasli_generic: expose peripheral_processors dictionary. Closes #1403
2019-12-10 10:30:06 +08:00
150a02117c
sayma_rtm: drive clk_src_ext_sel
2019-12-09 19:47:50 +08:00
307a6ca140
gth_ultrascale: make OBUFDS_GTE3 work
...
https://www.xilinx.com/support/answers/67919.html
2019-12-09 18:13:22 +08:00
2b5213b013
wrpll: constrain clocks
2019-12-09 12:26:44 +08:00
05e2e1899a
wrpll: update OBUFDS_GTE2 comment
...
Seems O can fan out simultaneously to transceiver and fabric.
Kasli is using ODIV2 for no particular reason.
2019-12-09 11:58:54 +08:00
4148efd2ee
wrpll: implement filters and connect to Si549
2019-12-09 11:47:29 +08:00
d43fe644f0
wrpll: stabilize DDMTDSamplerGTP
2019-12-09 11:47:14 +08:00
0499f83580
wrpll: helper clock sanity check
2019-12-08 23:46:33 +08:00
46a776d06e
sayma: introduce WRPLL on RTM
2019-12-08 15:30:00 +08:00
883310d83e
sayma_rtm: si5324 -> cdrclkc
2019-12-08 14:26:05 +08:00
57a5bea43a
sayma_rtm: support setting RTIO frequency
2019-12-08 11:45:31 +08:00
da9237de53
wrpll: support differential DDMTD inputs
2019-12-07 18:18:57 +08:00
7098854b0f
wrpll: share DDMTD counter
2019-12-04 19:05:56 +08:00
05c5fed07d
suservo: stray comma
2019-12-03 08:38:07 +00:00
56074cfffa
suservo: support operating with one urukul
...
implemented by wiring up the second Urukul to dummy pins
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-12-02 11:30:20 +01:00
86e1924493
kasli_generic: support external reference on masters
2019-11-30 07:34:41 +00:00
eb271f383b
wrpll: add DDMTD cores
2019-11-28 22:03:50 +08:00
2e55e39ac7
wrpll: use spaces to indent
2019-11-28 17:40:25 +08:00
354d82cfe3
wrpll: drive helper clock domain
2019-11-28 17:40:00 +08:00
68cab5be8c
si549: cleanups
2019-11-28 16:36:59 +08:00
4832bfb08c
wrpll: i2c functions, select_recovered_clock placeholder
2019-11-27 21:21:00 +08:00
c536f6c4df
sayma_amc: output ddmtd_rec_clk
2019-11-20 19:16:04 +08:00
ae50da09c4
drtio/gth_ultrascale: support OBUFDS_GTE3
2019-11-20 19:15:50 +08:00
fe0c324b38
sayma: integrate si549 core
2019-11-20 17:37:16 +08:00
fa41c946ea
wrpll: si549 fixes
2019-11-20 17:04:24 +08:00
c5dbab1929
gateware: move wrpll to drtio
2019-11-20 14:43:08 +08:00
David Nadlinger
bc3b55b1a8
gateware/eem: Force IOB=TRUE on Urukul SYNC output
...
Without this, the final register in the SYNC signal TTLClockGen
isn't (always) placed in the I/O tile, leading to more jitter
than necessary, and causing "double window" artefacts. See
sinara-hw/Urukul#16 for more details.
(Patch based on work by Weida Zhang, testing by various members
of the community in Oxford and elsewhere.)
2019-11-05 17:14:07 +08:00
98854473dd
sayma_amc: use all transceivers on master ( #1230 )
2019-11-02 12:12:32 +08:00
42af76326f
kasli: enlarge integrated CPU SRAM for DRTIO masters
...
Required by the bootloader netboot support.
2019-11-01 10:15:13 +08:00
228e44a059
sayma: enable Ethernet on DRTIO satellite variant
...
So that netboot can be used in bootloader.
2019-10-30 21:39:00 +08:00
dc71039934
sayma, metlino: increase integrated_sram_size on Ethernet-enabled variants
2019-10-30 21:36:00 +08:00
462cf5967e
bootloader: add netboot support
2019-10-30 21:23:42 +08:00
8fa3c6460e
sayma_amc: set direction of external TTL buffer according to RTIO PHY OE
2019-10-16 18:48:50 +08:00
37d0a5dc19
rtio/ttl: expose OE
2019-10-16 18:48:20 +08:00
bc060b7f01
style
2019-10-16 18:18:11 +08:00
21a1c6de3f
sayma: use SFP0 for DRTIO master
2019-10-16 17:53:40 +08:00
314d9b5d06
kasli: default to 125MHz frequency for DRTIO
...
This is the consistent and most common option. Sayma will also eventually move to it.
2019-10-08 12:59:52 +08:00
4df2c5d1fb
sayma: prepare for SYSREF align
...
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
2019-10-08 12:30:47 +08:00
03007b896e
sayma_amc: sma -> mcx
2019-10-07 20:31:35 +08:00
97a0dee3e8
jesd204: remove ibuf_disable
...
We use the MOSFET to mute the HMC7043 noise on hardware v2 instead.
2019-10-06 22:26:31 +08:00
f8e4cc37d0
sayma_rtm: reset and detect DACs
2019-10-06 20:15:27 +08:00
f62dc7e1d4
sayma: refactor JESD DAC channel groups
2019-10-06 20:15:09 +08:00
1c6c22fde9
sayma_amc: HMC830_REF moved to RTM side
2019-10-06 18:15:37 +08:00
e6ff44301b
sayma_amc: cleanup (v2.0 only)
2019-10-06 18:11:43 +08:00
e9b81f6e33
remove serwb
...
DRTIO is a better solution
2019-10-06 18:10:23 +08:00
7cd02d30b7
sayma_rtm_drtio: replace sayma_rtm
2019-10-06 17:59:53 +08:00
b3b85135a3
sayma_rtm_drtio: add DDMTD core, move specific cores out of SatelliteBase
2019-10-06 17:59:11 +08:00
346c985347
sayma_rtm_drtio: use artiq_sayma folder
2019-10-06 17:30:08 +08:00
4198033657
sayma_rtm_drtio: cleanup (v2.0 only)
2019-10-06 16:42:34 +08:00
5612b31860
sayma_rtm_drtio: add HMC clock chip and DAC control
2019-10-06 16:15:24 +08:00
