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wrpll: use spaces to indent

pull/1401/head
Sebastien Bourdeauducq 2019-11-28 17:40:25 +08:00
parent 354d82cfe3
commit 2e55e39ac7
1 changed files with 11 additions and 11 deletions
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22
artiq/gateware/drtio/wrpll/core.py
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@ -6,16 +6,16 @@ from artiq.gateware.drtio.wrpll.si549 import Si549
class WRPLL(Module, AutoCSR):
def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c):
self.helper_reset = CSRStorage(reset=1)
def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c):
self.helper_reset = CSRStorage(reset=1)
self.clock_domains.cd_helper = ClockDomain()
self.helper_reset.storage.attr.add("no_retiming")
self.specials += [
Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n,
o_O=self.cd_helper.clk),
AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
]
self.clock_domains.cd_helper = ClockDomain()
self.helper_reset.storage.attr.add("no_retiming")
self.specials += [
Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n,
o_O=self.cd_helper.clk),
AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
]
self.submodules.main_dcxo = Si549(main_dcxo_i2c)
self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
self.submodules.main_dcxo = Si549(main_dcxo_i2c)
self.submodules.helper_dcxo = Si549(helper_dxco_i2c)