65379b1f7a
conda: bump migen, misoc
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* xilinx ODDR2 SRTYPE
* flterm leak
* I/ODELAY VTC/reset sequencing
* sayma SDRAM clock buffer LOC
2018-03-19 19:58:52 +01:00
4b3f408143
sdram: simplify read level scan
2018-03-19 18:41:56 +00:00
845784c180
kusddrphy: use first and last tap that yield many valid reads
2018-03-19 17:54:26 +00:00
ed2e0c8b34
sayma/sdram/scan: test each tap 1024 times
2018-03-20 00:59:31 +08:00
hartytp
a27b5d88c2
Novogorny driver, remove unused imports ( #964 )
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* Novogorny driver, remove unused imports
* more unused imports
* oops, one final one!
2018-03-19 11:58:14 +01:00
7a7ff6d2dd
Merge pull request #963 from hartytp/kasli_zotino_sampler
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Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 …
2018-03-19 10:52:50 +01:00
Thomas Harty
37d431039d
Fix typos.
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Reduce ififo depth to 4 for Zotino.
2018-03-19 09:42:18 +00:00
whitequark
c86df8e13e
firmware: try to unstuck the I2C bus if it gets stuck.
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Fixes #957 .
2018-03-19 06:23:23 +00:00
Thomas Harty
c4fa44bc62
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock.
2018-03-18 00:25:43 +00:00
f39b7b33e8
ad5360: whitespace [nfc]
2018-03-17 18:51:17 +01:00
2eadb08f8c
Merge pull request #962 from hartytp/ad5360
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Fix AD5360 after migration to SPI2
2018-03-17 18:48:34 +01:00
ion
c1439bfd3b
Fix AD5360 after migration to SPI2
2018-03-17 11:37:11 +00:00
whitequark
c4bfc83b38
conda: mark the artiq-build output package as noarch, not toplevel.
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This also changes `noarch: python` to `noarch: generic` since
this is semantically correct; the bitstream/firmware packages
contain no Python code.
Fixes #960 .
2018-03-15 23:17:05 +00:00
whitequark
4b5a78e231
compiler: do not pass files to external tools while they are opened.
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This fixes access violations on Windows that are present both with
input and output files. For some reason, Cygwin-compiled binutils
did not exhibit this problem, but MSYS-compiled binutils do.
Fixes #961 .
2018-03-15 22:21:29 +00:00
whitequark
5cb2602021
artiq_devtool: flash gateware if -g is passed.
2018-03-15 08:33:53 +00:00
whitequark
9ea7d7a804
firmware: allow building without system UART.
2018-03-14 18:34:31 +00:00
whitequark
158ceb0881
artiq_devtool: add kasli target.
2018-03-14 18:13:13 +00:00
a315ecd10b
rtio/ttl_serdes_7series: reset IOSERDES ( #958 )
2018-03-14 09:01:29 +08:00
2fdc180601
dsp/fir: outputs reset_less (pipelined)
2018-03-13 17:11:50 +00:00
2edf65f57b
drtio: fix satellite minimum_coarse_timestamp clock domain ( #947 )
2018-03-13 00:20:57 +08:00
999ec40e79
bootloader: print gateware ident
2018-03-13 00:11:25 +08:00
2caeea6f25
update copyright year
2018-03-13 00:09:13 +08:00
1d081ed6c2
drtio: print diagnostic info on satellite write underflow ( #947 )
2018-03-12 23:41:19 +08:00
Florent Kermarrec
eb6e59b44c
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
2018-03-12 11:25:29 +01:00
6dfebd54dd
ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names
2018-03-12 10:37:33 +08:00
44277c5b7e
conda: bump migen/misoc
2018-03-11 10:11:42 +08:00
a04bd5a4fd
spi2: xfers take one more cycle until ~busy
2018-03-09 20:48:17 +01:00
Florent Kermarrec
5af4609053
libboard/sdram: limit write leveling scan to "512 - initial dqs taps delay" on ultrascale
2018-03-09 19:06:47 +01:00
Florent Kermarrec
a95cd423cc
libboard/sdram: add gap for write leveling
2018-03-09 18:53:57 +01:00
fc3d97f1f7
drtio: remove spurious multichannel transceiver clock constraints
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They used to cause (otherwise harmless) Vivado critical warnings.
2018-03-09 22:46:27 +08:00
caf7b14b55
kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code
2018-03-09 22:36:16 +08:00
e65e2421a3
conda: bump migen/misoc
2018-03-09 22:35:40 +08:00
Florent Kermarrec
8f6f83029c
libboard/sdram: add write/read leveling scan
2018-03-09 13:50:51 +01:00
Florent Kermarrec
b0b13be23b
libboard/sdram: rename read_delays to read_leveling
2018-03-09 09:23:20 +01:00
3fbcf5f303
drtio: remove TSC correction ( #40 )
2018-03-09 10:36:17 +08:00
e38187c760
drtio: increase default underflow margin. Closes #947
2018-03-09 00:49:24 +08:00
37f5f0d38d
examples: add DMA to Sayma DRTIO
2018-03-09 00:49:24 +08:00
Florent Kermarrec
8475c21c46
firmware/libboard/sdram: kusddrphy now use time mode for odelaye3/idelaye3, now reloading dqs delay_value (500ps) with software
2018-03-08 10:00:00 +01:00
8bd15d36c4
drtio: fix error CSR edge detection ( #947 )
2018-03-08 16:28:25 +08:00
0adbbd8ede
drtio: reset aux packet gateware after locking to recovered clock
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Closes #949
2018-03-08 15:41:13 +08:00
8bd85caafb
examples: fix Sayma DRTIO ref_period
2018-03-08 15:09:33 +08:00
37ec97eb28
ad9910/2: add sw invariant only when passed
2018-03-07 21:32:59 +01:00
82831a85b6
kasli/opticlock: add eem6 phys
2018-03-07 21:32:59 +01:00
5cc1d2a1d3
conda: bump migen, misoc
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* flterm leak
* kasli version
* sayma ddram
* ethernet clocking
* fifo dout reset_less
2018-03-07 17:17:30 +01:00
3a6566f949
rtio: judicious spray with reset_less=True
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Hoping to reduce rst routing difficulty and easier RTIO timing closure.
2018-03-07 14:57:18 +00:00
b0282fa855
spi2: reset configuration in rio_phy
2018-03-07 14:42:11 +00:00
7afb23e8be
runtime: demote dropped and malformed packets msgs to debug
2018-03-07 14:28:21 +01:00
4af7600b2d
Revert "LaneDistributor: try equivalent spread logic"
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This reverts commit 8b70db5f17
2018-03-07 11:34:51 +00:00
a6d1b030c1
RTIO: use TS counter in the correct CD
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artiq/m-labs#938
2018-03-07 11:34:42 +00:00
8b70db5f17
LaneDistributor: try equivalent spread logic
2018-03-07 11:34:42 +00:00
