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drtio: reset aux packet gateware after locking to recovered clock

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Closes #949
This commit is contained in:
Sebastien Bourdeauducq 2018-03-08 15:41:05 +08:00
parent 8bd85caafb
commit 0adbbd8ede
2 changed files with 12 additions and 0 deletions
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11
artiq/firmware/libdrtioaux/lib.rs
View File

@ -269,6 +269,17 @@ pub mod hw {
use super::*;
use std::io::Cursor;
pub fn reset(linkno: u8) {
let linkno = linkno as usize;
unsafe {
// clear buffer first to limit race window with buffer overflow
// error. We assume the CPU is fast enough so that no two packets
// will be received between the buffer and the error flag are cleared.
(board::csr::DRTIO[linkno].aux_rx_present_write)(1);
(board::csr::DRTIO[linkno].aux_rx_error_write)(1);
}
}
fn rx_has_error(linkno: u8) -> bool {
let linkno = linkno as usize;
unsafe {

1
artiq/firmware/satman/main.rs
View File

@ -237,6 +237,7 @@ fn startup() {
info!("link is up, switching to recovered clock");
si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
si5324::siphaser::calibrate_skew(32).expect("failed to calibrate skew");
drtioaux::hw::reset(0);
drtio_reset(false);
drtio_reset_phy(false);
while drtio_link_rx_up() {