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6,228 Commits 13 Branches 35 Tags 28 MiB
Commit Graph

180 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 69d060b639 drtio: fix satellite i_status handling 2018-09-19 20:57:21 +08:00
Sebastien Bourdeauducq ec62eb9373 drtio: minor cleanup 2018-09-07 17:51:38 +08:00
Robert Jördens eb9e9634df siphaser: support 125 MHz rtio clk 
keep the phase shift increment/decrement at 1/(56*8) rtio_clk
cycles
 2018-08-29 17:53:48 +00:00
Sebastien Bourdeauducq e2a49ce368 drtio: support external IBUFDS_GTE3 2018-08-07 20:52:45 +08:00
Sebastien Bourdeauducq c1db02a351 drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin 
Precaution against HMC7043 noise issues.
 2018-06-21 22:56:07 +08:00
Sebastien Bourdeauducq e29536351d drtio: resync SYSREF when TSC is loaded 2018-06-21 17:00:32 +08:00
Sebastien Bourdeauducq 9142a5ab8a rtio: expose coarse timestamp in RTIO and DRTIO satellite cores 2018-06-20 17:39:54 +08:00
Chris Ballance 07d4145a35 correct documented siphaser VCO frequency [NFC] 2018-06-04 20:53:43 +08:00
Sebastien Bourdeauducq 2426fea3f2 siphaser: support external reference for the freerunning 150MHz 2018-05-12 22:57:11 +08:00
Sebastien Bourdeauducq 2edf65f57b drtio: fix satellite minimum_coarse_timestamp clock domain (#947) 2018-03-13 00:20:57 +08:00
Sebastien Bourdeauducq 1d081ed6c2 drtio: print diagnostic info on satellite write underflow (#947) 2018-03-12 23:41:19 +08:00
Sebastien Bourdeauducq 3fbcf5f303 drtio: remove TSC correction (#40) 2018-03-09 10:36:17 +08:00
Sebastien Bourdeauducq e38187c760 drtio: increase default underflow margin. Closes #947 2018-03-09 00:49:24 +08:00
Sebastien Bourdeauducq 8bd15d36c4 drtio: fix error CSR edge detection (#947) 2018-03-08 16:28:25 +08:00
Sebastien Bourdeauducq 916197c4d7 siphaser: cleanup 2018-03-07 11:15:44 +08:00
Sebastien Bourdeauducq f7aba6b570 siphaser: fix phase_shift_done CSR 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq acfd9db185 siphaser: minor cleanup 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq 7d98864b31 sayma: enable siphaser 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq c34d00cbc9 drtio: implement Si5324 phaser gateware and partial firmware support 2018-03-07 10:57:30 +08:00
Florent Kermarrec 5b3d6d57e2 drtio/gth: power down rx on restart (seems to make link initialization reliable) 2018-03-06 11:49:28 +01:00
Florent Kermarrec 64b05f07bb drtio/gth: use parameters from Xilinx transceiver wizard 2018-03-06 11:02:15 +01:00
Florent Kermarrec 45f1e5a70e drtio/gth: cleanup import 2018-03-06 10:56:07 +01:00
Sebastien Bourdeauducq 6aaa8bf9d9 drtio: fix link error generation 2018-03-04 23:20:13 +08:00
Sebastien Bourdeauducq 928d5dc9b3 drtio: raise RTIOLinkError if operation fails due to link lost (#942) 2018-03-04 01:02:53 +08:00
Florent Kermarrec 2896dc619b drtio/transceiver/gth: fix multilane 2018-02-28 14:15:40 +01:00
Florent Kermarrec 1f0d955ce4 drtio/transceiver/gtp: implement tx multi lane phase alignment sequence 2018-02-27 12:32:25 +01:00
Florent Kermarrec 5b0f9cc6fd drtio/transceiver/gth: fix single transceiver case 2018-02-23 12:15:47 +01:00
Florent Kermarrec b4ba71c7a4 drtio/transceiver/gth: implement tx multi lane phase alignment sequence (fix merge issue...) 2018-02-23 08:37:05 +01:00
Florent Kermarrec 820c834251 drtio/transceiver/gth: implement tx multi lane phase alignment sequence 2018-02-22 22:14:15 +01:00
Sebastien Bourdeauducq fa0d929b4d drtio: reorganize RX synchronizers 2018-02-22 15:21:23 +08:00
Sebastien Bourdeauducq f060d6e1b3 drtio: increase A7 clock aligner check period 2018-02-20 18:50:35 +08:00
Sebastien Bourdeauducq f15b4bdde7 style 2018-02-20 18:47:59 +08:00
Sebastien Bourdeauducq ad2c9590d0 drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
Sebastien Bourdeauducq 52049cf36a drtio: add Xilinx RX synchronizer 2018-02-19 17:49:43 +08:00
Florent Kermarrec f5831af535 drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down 2018-02-19 10:03:19 +01:00
Florent Kermarrec 89a158c0c9 drtio/transceiver/gtp_7series_init: remove dead code 2018-02-19 10:02:23 +01:00
Florent Kermarrec 782051f474 drtio/transceiver/gtp_7series_init: add no retiming on gtp resets 2018-02-19 09:59:50 +01:00
Sebastien Bourdeauducq 94c20dfd4d drtio: fix misleading GenericRXSynchronizer comment 2018-02-19 00:47:54 +08:00
Sebastien Bourdeauducq 83abdd283a drtio: signal stable clock input to transceiver 2018-02-18 22:29:30 +08:00
Florent Kermarrec bfdda340fd drtio/transceiver/gtp_7series: use parameters from xilinx wizard 2018-02-13 00:23:59 +01:00
Florent Kermarrec 180c28551d drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable) 2018-02-09 20:17:02 +01:00
Sebastien Bourdeauducq d6157514c7 gtp_7series: flexible QPLL channel selection 2018-01-23 12:03:09 +08:00
Sebastien Bourdeauducq 98a5607634 gtp_7series: set clock muxes correctly for second QPLL channel 2018-01-23 10:39:20 +08:00
Sebastien Bourdeauducq 25fee1a0bb gtp_7series: use QPLL second channel 2018-01-23 10:15:49 +08:00
Sebastien Bourdeauducq 626075cbc1 gtp_7series: simplify TX clocking 2018-01-23 09:49:23 +08:00
Sebastien Bourdeauducq 401e57d41c gtp_7series: fix nchannels assert 2018-01-23 01:28:01 +08:00
Sebastien Bourdeauducq 5198c224a2 sayma,kasli: use new pin names 2018-01-22 11:51:07 +08:00
Florent Kermarrec d27727968c add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
Sebastien Bourdeauducq dc593ec0f0 Merge branch 'rtio-sed' into sed-merge 2018-01-10 12:04:54 +08:00
Sebastien Bourdeauducq 6e0288e568 drtio: fix GTH CPLL reset 2017-12-30 12:14:36 +08:00