d0b8818688
Add 125 MHz from 80 MHz reference option to rtio clocking
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-04-13 14:57:24 +08:00
ciciwu
67ca48fa84
manual: fix formatting ( #1865 )
2022-03-08 19:03:47 +08:00
9b1d7e297d
runtime: clock input specification improvements
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closes #1735
2021-10-28 16:21:51 +08:00
1e869aedd3
docs: clarify rtio_clock=e req's and use case
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This regularly leads to people misunderstanding the setting.
Mentioning the Si5324 specifically or Urukul synchronization doesn't help constraining or explaining the feature, its consequences and requirements.
Despite being non-standard this feature is also generally not sufficient to achieve cross-device determinism as the other devices need to be made deterministic as well.
2021-08-03 11:36:04 +02:00
a947867887
runtime: support Kasli Si5324 bypass via rtio_clock=e
2019-06-14 15:48:05 +08:00
7e7f463d11
manual: fix fs.com link
2019-05-07 22:19:23 +08:00
4e230bb768
manual: update core device section on Kasli
2019-05-07 20:19:13 +08:00
766d87f626
doc: artiq_coreconfig → artiq_coremgmt config. Closes #1111
2018-07-20 11:59:07 +08:00
3168b193e6
kc705: remove Zotino and Urukul
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* use Kasli instead for using EEMs
* code required outdated VHDCI adapter 1.0
2018-07-17 17:48:57 +08:00
b10d3ee4b4
make RTIO clock switch optional and simplify
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Kasli no longer has an internal RTIO clock.
Switching clocks dynamically is no longer supported.
2018-05-18 17:41:34 +08:00
7986391422
manual: update Kasli section
2018-02-21 12:04:14 +08:00
6c4681e7d2
manual: fix minor errors
2018-02-21 11:57:57 +08:00
21cd24fe80
manual: add section on Kasli/opticlock
2018-01-15 15:13:24 +01:00
94b84ebe7c
kc705_dds: add urukul spi/ttl channels
2018-01-02 13:20:48 +01:00
569484f888
remove phaser, adapt SAWG example to Sayma
2017-12-14 18:49:27 +08:00
b89929565c
manual: fix formatting problem
2017-11-25 14:46:31 +08:00
33d339947c
doc: add information on how to connect Zotino
2017-11-01 20:20:42 +08:00
d80cf8d59d
kc705: add TTLs and shift register driver for FMC DIO
2017-10-31 23:14:39 +08:00
5803ac9998
gateware: add Zotino SPI to NIST CLOCK target
2017-10-23 15:04:30 +08:00
43d551f1d8
README_PHASER: integrate into board port docs
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* rewrite setup commands for usage of artiq-dev metapackage
* integrate with rest of installation documentation
* move contents of README_PHASER to core_device.rst
* closes #815
2017-08-29 16:15:51 +02:00
94ee48860a
doc: fix phaser channel number statement
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closes #781
2017-07-15 20:24:50 +02:00
mntng
40ca951750
kc705: add SPI bus for memory card
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This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
9ab63920e0
Remove Pipistrello support
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Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
f7e8961ab0
Merge branch 'master' into phaser
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* master: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
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2016-11-21 17:29:39 +01:00
93c310dfa5
pipistrello: add some inputs
2016-11-21 23:43:41 +08:00
whitequark
6aa5d9f6c6
Remove last vestiges of nist_qc1.
2016-11-21 15:36:22 +00:00
whitequark
5e8888d5f3
Fully drop AD9858 and kc705-nist_qc1 support ( closes #576 ).
2016-11-21 15:14:17 +00:00
18d18b6685
phaser: add sync ttl input for monitoring
2016-10-10 17:13:23 +02:00
4d87f0e9e0
phaser: instantiate jesd204b core, wire up
2016-10-06 14:44:22 +02:00
c54b6e2f3c
phaser: add README
2016-10-05 19:24:34 +02:00
4a0eaf0f95
phaser: add jesd204b rtio dds
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gateware: add jesd204b awg
gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce
sawg: kernel support and docs
sawg: coredevice api fixes
sawg: example ddb/experiment
phaser: add conda package
examples/phaser: typo
sawg: adapt tests, fix accu stb
sawg: tweak dds parameters
sawg: move/adapt/extend tests
sawg: test phy, refactor
phaser: non-rtio spi
phaser: target cli update
phaser: ad9154-fmc-ebz pins
phaser: reorganize fmc signal naming
phaser: add test mode stubs
phaser: txen is LVTTL
phaser: clk spi xfer test
phaser: spi for ad9154 and ad9516
phaser: spi tweaks
ad9154: add register map from ad9144.xml
ad9516: add register map from ad9517.xml and manual adaptation
ad9154_reg: just generate getter/setter macros as well
ad9154: reg WIP
ad9154: check and fix registers
kc705: single ended rtio_external_clk
use single ended user_sma_clk_n instead of p/n to free up one clock sma
kc705: mirror clk200 at user_sma_clock_p
ad9516_regs.h: fix B_COUNTER_MSB
phase: wire up clocking differently
needs patched misoc
kc705: feed rtio_external_clock directly
kc705: remove rtio_external_clk for phaser
phaser: spi tweaks
ad9516: some startup
ad9516_reg fixes
phaser: setup ad9516 for supposed 500 MHz operation
ad9516: use full duplex spi
ad9154_reg: add CONFIG_REG_2
ad9154_reg: fixes
phaser: write some ad9154 config
ad9154_reg: fixes
ad9154: more init, and human readable setup
ad9154/ad9516: merge spi support
ad9154: status readout
Revert "kc705: remove rtio_external_clk for phaser"
This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.
Revert "kc705: feed rtio_external_clock directly"
This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.
Revert "phase: wire up clocking differently"
This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.
Revert "kc705: mirror clk200 at user_sma_clock_p"
This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.
Revert "kc705: single ended rtio_external_clk"
This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.
ad9516: 2000 MHz clock
phaser: test clock dist
phaser: test freqs
ad9154: iostandards
phaser: drop clock monitor
phaser: no separate i2c
phaser: drive rtio from refclk, wire up sysref
phaser: ttl channel for sync
ad9154: 4x interp, status, tweaks
phaser: sync/sysref 33V banks
phaser: sync/sysref LVDS_25 inputs are VCCO tolerant
phaser: user input-only ttls
phaser: rtio fully from refclk
ad9154: reg name usage fix
ad9154: check register modifications
Revert "ad9154: check register modifications"
This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.
ad9154: fix status code
ad9154: addrinc, recal serdes pll
phaser: coredevice, example tweaks
sawg: missing import
sawg: type fixes
ad9514: move setup functions
ad9154: msb first also decreasing addr
phaser: use sys4x for rtio internal ref
phaser: move init code to main
phaser: naming cleanup
phaser: cleanup pins
phaser: move spi to kernel cpu
phaser: kernel support for ad9154 spi
ad9154: add r/w methods
ad9154: need return annotations
ad9154: r/w methods are kernels
ad9154_reg: portable helpers
phaser: cleanup startup kernel
ad9154: status test
ad9154: prbs test
ad9154: move setup, document
phaser: more documentation
2016-10-05 16:17:50 +02:00
4ef5eb2644
doc: move VADJ, closes #554
2016-09-09 18:40:58 +08:00
2912515e5c
doc: add warning about pipistrello current draw
2016-06-11 10:26:35 -06:00
ca9724f517
doc: add core device comms details
2016-06-11 10:01:15 -06:00
e8aadd0a1a
doc: document common KC705 problems. Closes #450
2016-06-03 23:20:38 -04:00
dhslichter
141edb521a
qc2: swap SPI/TTL, all TTL lines are now In+Out compatible
2016-05-19 10:42:03 +08:00
dhslichter
f395a630e0
Updated qc2 pinouts for SPI and 2x DDS bus, update docs
2016-04-13 18:38:34 +08:00
05317a9259
manual: QC2 FMC voltage
2016-03-31 10:47:16 +08:00
878ab9a39b
manual: document DDS and SPI RTIO channels
2016-03-10 22:38:49 +08:00
f0b0b1bac7
support for multiple DDS buses (untested)
2016-03-09 17:12:50 +08:00
f33baf339f
pipistrello: drop ttls on pmod, add leds back in
2016-03-08 23:34:51 +01:00
f39208c95a
pipistrello: try with fewer leds/pmod ttl
2016-03-08 22:10:47 +01:00
104d641c59
pipistrello: move the spi channel like kc705
2016-03-08 13:30:05 +01:00
40c1cde2e2
doc: kc705.clock: add spi bus mappings ( closes #321 )
2016-03-08 13:28:32 +01:00
9898cb14db
doc: add pipistrello spi bus
2016-03-08 13:18:55 +01:00
e23e91f8ac
doc: add pipistrello pmod ttl channels
2016-03-08 13:13:33 +01:00
2770d9c729
doc: I2C/QC2
2016-03-05 19:02:03 +08:00
2cc1dfaee3
kc705: move ttl channels together again, update doc
2016-03-01 19:40:32 +01:00
5fad570f5e
targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
2016-03-01 00:35:26 +08:00
0151ac55ff
ppp: update documentation
2016-01-25 12:29:05 -07:00
