M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

runtime: support Kasli Si5324 bypass via rtio_clock=e

This commit is contained in:
Sebastien Bourdeauducq 2019-06-14 15:48:05 +08:00
parent 66a66b03b4
commit a947867887
2 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
artiq/firmware/runtime/rtio_clocking.rs
View File

@ -137,7 +137,12 @@ fn setup_si5324_as_synthesizer() {
pub fn init() {
#[cfg(si5324_as_synthesizer)]
setup_si5324_as_synthesizer();
{
match get_rtio_clock_cfg() {
RtioClock::Internal => setup_si5324_as_synthesizer(),
RtioClock::External => si5324::bypass(si5324::Input::Ckin2)
}
}
#[cfg(has_drtio)]
unsafe {

3
doc/manual/core_device.rst
View File

@ -164,5 +164,6 @@ See :mod:`artiq.coredevice.i2c` for more details.
Clocking
++++++++
The KC705 supports an internal 125MHz RTIO clock (based on its crystal oscillator) and an external clock, that can be selected using the ``rtio_clock`` configuration entry.
The KC705 supports an internal 125MHz RTIO clock (based on its crystal oscillator) and an external clock, that can be selected using the ``rtio_clock`` configuration entry. Valid values are ``i`` and ``e``, and the default is ``i``. The selected option can be observed in the core device boot logs.
On Kasli, when set to ``e``, the ``rtio_clock`` setting overrides the built-in (and variant-dependent) Si5324 synthesizer configuration and disables the Si5324. The user must apply a clock at the RTIO frequency on the Kasli front panel SMA. As the Si5324 is bypassed in this mode, its skew is deterministic, which is useful to distribute clocks externally to Kasli and Urukul when Urukul phase synchronization is desired.