Commit Graph

34 Commits

Author SHA1 Message Date
347e858ece helloworld -> helloworld_kintex7 2019-04-26 16:56:47 +08:00
05974f272d bump minerva 2019-04-22 14:40:17 +08:00
dd64f92754 bump nmigen 2019-04-22 14:40:04 +08:00
2bd819fcbe roundrobin: use nmigen zero-width signals 2019-04-18 11:58:51 +08:00
e14031fba6 add round-robin arbiter 2019-04-17 20:18:41 +08:00
034ecc4d99 nmigen: run tests in verbose mode 2019-04-17 16:08:37 +08:00
4dd024942e nmigen: bump 2019-04-17 16:08:18 +08:00
e3f47815e5 rust: add riscv32i 2019-04-09 00:48:19 +08:00
25fe837684 use upstream rust/llvm 2019-04-09 00:09:58 +08:00
c3992220e5 rustc: fix crates compilation 2019-04-07 23:16:00 +08:00
da982a60cc rustc: add libxml2 dep 2019-04-07 00:45:02 +08:00
0ef16ba90c llvm: use more up-to-date upstream, build for riscv 2019-04-06 21:25:34 +08:00
52dbb6275f rust: fix riscv target name 2019-04-06 20:06:09 +08:00
96b7248514 rustc: use more up-to-date upstream, build for riscv 2019-04-06 19:16:34 +08:00
b913a92a82 add rustc (WIP) 2019-04-06 18:23:31 +08:00
298514fe0a move fetch-llvm-clang.nix into llvm-hx.nix 2019-04-06 15:20:49 +08:00
1bf9b5eb2b add VexRiscv 2019-04-05 18:58:11 +08:00
584dba9ed0 add scala-spinalhdl 2019-04-04 23:44:07 +08:00
e56d2ad3c8 style 2019-04-04 23:43:46 +08:00
466d85e719 reorganize 2019-04-01 11:05:08 +08:00
3dd10e6b9b add simple test for UART 2019-03-28 19:39:30 +08:00
472114c136 add binutils 2019-03-27 16:55:36 +08:00
ed53324019 add LLVM and Clang 2019-03-27 16:42:07 +08:00
7bac1cd3ef minor cleanup 2019-03-25 23:41:22 +08:00
e047e69f78 fix helloworld.nix 2019-03-25 23:37:16 +08:00
b22aff308a add nix-build results to .gitignore 2019-03-25 23:36:52 +08:00
ca0707fa88 print hello world on UART 2019-03-25 16:50:01 +08:00
b2bcbd7048 add UART example 2019-03-25 16:10:07 +08:00
38ccee5c01 reorganize Nix files to expose lib functions and derivations properly 2019-03-25 16:07:50 +08:00
0f512c762b use patched yosys 2019-03-25 10:12:18 +08:00
602ccc0f47 vivado: do not import nixpkgs by default 2019-03-25 10:11:51 +08:00
6082e5a1de add vivado buildBitstream derivation 2019-03-19 23:00:36 +08:00
55e12d3185 add component library with UART 2019-03-19 16:52:02 +08:00
cf6ebc9953 package minerva and dependencies 2019-03-19 15:46:28 +08:00