M-Labs/HeavyX
6
1
Fork 0
Code Issues Pull Requests Releases Wiki Activity
Next-generation FPGA SoC toolkit
2 Commits 2 Branches 0 Tags 412 KiB
Nix 60.4%
Python 29.9%
Diff 7.1%
Rust 2.4%
RPC 0.2%
55e12d3185
Go to file
Sebastien Bourdeauducq 55e12d3185 add component library with UART
2019-03-19 16:52:02 +08:00
heavycomps add component library with UART 2019-03-19 16:52:02 +08:00
default.nix add component library with UART 2019-03-19 16:52:02 +08:00
heavycomps.nix add component library with UART 2019-03-19 16:52:02 +08:00
jtagtap.nix package minerva and dependencies 2019-03-19 15:46:28 +08:00
minerva.nix package minerva and dependencies 2019-03-19 15:46:28 +08:00
nmigen.nix package minerva and dependencies 2019-03-19 15:46:28 +08:00