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Next-generation FPGA SoC toolkit
14 Commits
2 Branches
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410 KiB
Nix 60.4%
Python 29.9%
Diff 7.1%
Rust 2.4%
RPC 0.2%
 
 
 
 
 
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Sebastien Bourdeauducq 3dd10e6b9b add simple test for UART 2019-03-28 19:39:30 +08:00
examples minor cleanup 2019-03-25 23:41:22 +08:00
heavycomps add simple test for UART 2019-03-28 19:39:30 +08:00
.gitignore add nix-build results to .gitignore 2019-03-25 23:36:52 +08:00
binutils.nix add binutils 2019-03-27 16:55:36 +08:00
default.nix reorganize Nix files to expose lib functions and derivations properly 2019-03-25 16:07:50 +08:00
derivations.nix add binutils 2019-03-27 16:55:36 +08:00
fetch-llvm-clang.nix add LLVM and Clang 2019-03-27 16:42:07 +08:00
heavycomps.nix add component library with UART 2019-03-19 16:52:02 +08:00
jtagtap.nix package minerva and dependencies 2019-03-19 15:46:28 +08:00
llvm-hx.nix add LLVM and Clang 2019-03-27 16:42:07 +08:00
minerva.nix package minerva and dependencies 2019-03-19 15:46:28 +08:00
nmigen.nix package minerva and dependencies 2019-03-19 15:46:28 +08:00
release.nix reorganize Nix files to expose lib functions and derivations properly 2019-03-25 16:07:50 +08:00
vivado.nix reorganize Nix files to expose lib functions and derivations properly 2019-03-25 16:07:50 +08:00
yosys.nix use patched yosys 2019-03-25 10:12:18 +08:00
yosys_726.patch use patched yosys 2019-03-25 10:12:18 +08:00