use patched yosys
This commit is contained in:
parent
602ccc0f47
commit
0f512c762b
@ -1,6 +1,8 @@
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{ pkgs ? import <nixpkgs> {}}:
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rec {
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nmigen = pkgs.callPackage ./nmigen.nix {};
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yosys = pkgs.callPackage ./yosys.nix {};
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symbiyosys = pkgs.symbiyosys.override { inherit yosys; };
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nmigen = pkgs.callPackage ./nmigen.nix { inherit yosys; };
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jtagtap = pkgs.callPackage ./jtagtap.nix { inherit nmigen; };
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minerva = pkgs.callPackage ./minerva.nix { inherit nmigen; inherit jtagtap; };
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heavycomps = pkgs.callPackage ./heavycomps.nix { inherit nmigen; };
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78
yosys.nix
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78
yosys.nix
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@ -0,0 +1,78 @@
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{ stdenv, fetchFromGitHub
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, pkgconfig, bison, flex
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, tcl, readline, libffi, python3
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, protobuf
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}:
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with builtins;
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stdenv.mkDerivation rec {
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name = "yosys-${version}";
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version = "2019.03.25hx";
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srcs = [
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(fetchFromGitHub {
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owner = "yosyshq";
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repo = "yosys";
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rev = "ccfa2fe01cffcc4d23bc989e558bd33addfea58e";
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sha256 = "05raqky4l2na8nyim51g8fzv49mg5f3p64lpdr7slxg74s270zry";
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name = "yosys";
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})
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# NOTE: the version of abc used here is synchronized with
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# the one in the yosys Makefile of the version above;
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# keep them the same for quality purposes.
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(fetchFromGitHub {
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owner = "berkeley-abc";
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repo = "abc";
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rev = "2ddc57d8760d94e86699be39a628178cff8154f8";
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sha256 = "0da7nnnnl9cq2r7s301xgdc8nlr6hqmqpvd9zn4b58m125sp0scl";
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name = "yosys-abc";
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})
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];
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sourceRoot = "yosys";
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enableParallelBuilding = true;
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nativeBuildInputs = [ pkgconfig ];
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buildInputs = [ tcl readline libffi python3 bison flex protobuf ];
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makeFlags = [ "ENABLE_PROTOBUF=1" ];
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patchPhase = ''
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patch -p1 < ${./yosys_726.patch}
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substituteInPlace ../yosys-abc/Makefile \
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--replace 'CC := gcc' ""
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substituteInPlace ./Makefile \
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--replace 'CXX = clang' "" \
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--replace 'ABCMKARGS = CC="$(CXX)"' 'ABCMKARGS =' \
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--replace 'echo UNKNOWN' 'echo ${substring 0 10 (elemAt srcs 0).rev}'
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'';
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preBuild = ''
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chmod -R u+w ../yosys-abc
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ln -s ../yosys-abc abc
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make config-${if stdenv.cc.isClang or false then "clang" else "gcc"}
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echo 'ABCREV := default' >> Makefile.conf
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makeFlags="PREFIX=$out $makeFlags"
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# we have to do this ourselves for some reason...
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(cd misc && ${protobuf}/bin/protoc --cpp_out ../backends/protobuf/ ./yosys.proto)
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'';
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meta = {
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description = "Framework for RTL synthesis tools";
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longDescription = ''
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Yosys is a framework for RTL synthesis tools. It currently has
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extensive Verilog-2005 support and provides a basic set of
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synthesis algorithms for various application domains.
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Yosys can be adapted to perform any synthesis job by combining
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the existing passes (algorithms) using synthesis scripts and
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adding additional passes as needed by extending the yosys C++
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code base.
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'';
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homepage = http://www.clifford.at/yosys/;
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license = stdenv.lib.licenses.isc;
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maintainers = with stdenv.lib.maintainers; [ shell thoughtpolice ];
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platforms = stdenv.lib.platforms.unix;
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};
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}
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399
yosys_726.patch
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399
yosys_726.patch
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@ -0,0 +1,399 @@
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diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
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index 83d83f48..ef6f102c 100644
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--- a/backends/verilog/verilog_backend.cc
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+++ b/backends/verilog/verilog_backend.cc
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@@ -25,6 +25,7 @@
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/sigtools.h"
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+#include "kernel/modtools.h"
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#include <string>
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#include <sstream>
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#include <set>
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@@ -33,15 +34,17 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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-bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit;
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+bool verbose, norename, noattr, attr2comment, noexpr, nodec, noinline, nohex, nostr, defparam, decimal, siminit;
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int auto_name_counter, auto_name_offset, auto_name_digits;
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std::map<RTLIL::IdString, int> auto_name_map;
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std::set<RTLIL::IdString> reg_wires, reg_ct;
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+std::map<RTLIL::Wire*, int> proc_consumed_wires;
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std::string auto_prefix;
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RTLIL::Module *active_module;
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dict<RTLIL::SigBit, RTLIL::State> active_initdata;
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SigMap active_sigmap;
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+ModIndex active_modindex;
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void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
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{
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@@ -183,6 +186,72 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name)
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return true;
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}
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+bool can_inline_cell_expr(RTLIL::Cell *cell)
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+{
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+ static pool<IdString> inlinable_cells = {
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+ "$not", "$pos", "$neg",
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+ "$and", "$or", "$xor", "$xnor",
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+ "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
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+ "$shl", "$shr", "$sshl", "$sshr",
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+ "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
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+ "$add", "$sub", "$mul", "$div", "$mod", "$pow",
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+ "$logic_not", "$logic_and", "$logic_or",
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+ "$mux"
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+ };
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+
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+ if (noinline)
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+ return false;
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+
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+ if (!inlinable_cells.count(cell->type))
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+ return false;
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+
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+ const RTLIL::SigSpec &output = cell->getPort("\\Y");
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+ if (!output.is_wire())
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+ return false;
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+
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+ RTLIL::Wire *output_wire = output.as_wire();
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+ if (output_wire->port_id || (!noattr && output_wire->attributes.size()))
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+ return false;
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+
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+ pool<ModIndex::PortInfo> ports = active_modindex.query_ports(output[0]);
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+ if (proc_consumed_wires[output_wire] == 1 && ports.size() == 1)
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+ return true;
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+
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+ if (proc_consumed_wires[output_wire] == 0 && ports.size() == 2)
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+ {
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+ auto port1 = ports.pop();
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+ auto port2 = ports.pop();
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+ return port1.cell->getPort(port1.port).size() ==
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+ port2.cell->getPort(port2.port).size();
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+ }
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+
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+ return false;
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+}
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+
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+bool can_inline_wire(RTLIL::Wire *wire)
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+{
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+ if (noinline)
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+ return false;
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+
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+ RTLIL::SigSpec wire_spec = RTLIL::SigSpec(wire);
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+ if (wire_spec.empty())
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+ return false;
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+
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+ pool<ModIndex::PortInfo> ports = active_modindex.query_ports(wire_spec[0]);
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+ if (ports.size() > 2)
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+ return false;
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+
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+ for (auto &port_info : ports)
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+ {
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+ if (port_info.cell->name[0] == '$' && port_info.port == "\\Y")
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+ {
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+ if (can_inline_cell_expr(port_info.cell))
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+ return true;
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+ }
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+ }
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+ return false;
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+}
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+
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void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false, bool escape_comment = false)
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{
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if (width < 0)
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@@ -313,13 +382,29 @@ void dump_reg_init(std::ostream &f, SigSpec sig)
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}
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}
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+bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell, bool do_inline);
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+
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void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decimal = false)
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{
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if (chunk.wire == NULL) {
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dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal);
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} else {
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if (chunk.width == chunk.wire->width && chunk.offset == 0) {
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- f << stringf("%s", id(chunk.wire->name).c_str());
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+ if (can_inline_wire(chunk.wire))
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+ {
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+ f << "(";
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+ pool<ModIndex::PortInfo> ports = active_modindex.query_ports(SigSpec(chunk)[0]);
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+ for (auto &port_info : ports)
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+ {
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+ if (port_info.port == "\\Y")
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+ dump_cell_expr(f, "", port_info.cell, true);
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+ }
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+ f << ")";
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+ }
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+ else
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+ {
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+ f << stringf("%s", id(chunk.wire->name).c_str());
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+ }
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} else if (chunk.width == 1) {
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if (chunk.wire->upto)
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f << stringf("%s[%d]", id(chunk.wire->name).c_str(), (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset);
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@@ -372,6 +457,9 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
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void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
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{
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+ if (can_inline_wire(wire))
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+ return;
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+
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dump_attributes(f, indent, wire->attributes);
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#if 0
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if (wire->port_input && !wire->port_output)
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@@ -464,30 +552,54 @@ no_special_reg_name:
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}
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}
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-void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op)
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+void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op, bool do_inline)
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{
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- f << stringf("%s" "assign ", indent.c_str());
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- dump_sigspec(f, cell->getPort("\\Y"));
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- f << stringf(" = %s ", op.c_str());
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+ if (!do_inline)
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+ {
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+ f << stringf("%s" "assign ", indent.c_str());
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+ dump_sigspec(f, cell->getPort("\\Y"));
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+ f << stringf(" = ");
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+ }
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+ f << stringf("%s ", op.c_str());
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dump_attributes(f, "", cell->attributes, ' ');
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dump_cell_expr_port(f, cell, "A", true);
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- f << stringf(";\n");
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+ if (!do_inline)
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+ {
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+ f << stringf(";\n");
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+ }
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}
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-void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op)
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+void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op, bool do_inline)
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{
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- f << stringf("%s" "assign ", indent.c_str());
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- dump_sigspec(f, cell->getPort("\\Y"));
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- f << stringf(" = ");
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+ if (!do_inline)
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+ {
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+ f << stringf("%s" "assign ", indent.c_str());
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+ dump_sigspec(f, cell->getPort("\\Y"));
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+ f << stringf(" = ");
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+ }
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+ else
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+ {
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+ f << stringf("(");
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+ }
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dump_cell_expr_port(f, cell, "A", true);
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f << stringf(" %s ", op.c_str());
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dump_attributes(f, "", cell->attributes, ' ');
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dump_cell_expr_port(f, cell, "B", true);
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- f << stringf(";\n");
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+ if (!do_inline)
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+ {
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+ f << stringf(";\n");
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+ }
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+ else
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+ {
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+ f << stringf(")");
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+ }
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}
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-bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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+bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell, bool do_inline)
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{
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+ if (can_inline_cell_expr(cell) && !do_inline)
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+ return true;
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+
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if (cell->type == "$_NOT_") {
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, cell->getPort("\\Y"));
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@@ -658,9 +770,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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}
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#define HANDLE_UNIOP(_type, _operator) \
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- if (cell->type ==_type) { dump_cell_expr_uniop(f, indent, cell, _operator); return true; }
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+ if (cell->type ==_type) { dump_cell_expr_uniop(f, indent, cell, _operator, do_inline); return true; }
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#define HANDLE_BINOP(_type, _operator) \
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- if (cell->type ==_type) { dump_cell_expr_binop(f, indent, cell, _operator); return true; }
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+ if (cell->type ==_type) { dump_cell_expr_binop(f, indent, cell, _operator, do_inline); return true; }
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HANDLE_UNIOP("$not", "~")
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HANDLE_UNIOP("$pos", "+")
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@@ -756,16 +868,30 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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if (cell->type == "$mux")
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{
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- f << stringf("%s" "assign ", indent.c_str());
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- dump_sigspec(f, cell->getPort("\\Y"));
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- f << stringf(" = ");
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+ if (!do_inline)
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+ {
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+ f << stringf("%s" "assign ", indent.c_str());
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+ dump_sigspec(f, cell->getPort("\\Y"));
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+ f << stringf(" = ");
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+ }
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+ else
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+ {
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+ f << stringf("(");
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+ }
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dump_sigspec(f, cell->getPort("\\S"));
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f << stringf(" ? ");
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dump_attributes(f, "", cell->attributes, ' ');
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dump_sigspec(f, cell->getPort("\\B"));
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f << stringf(" : ");
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dump_sigspec(f, cell->getPort("\\A"));
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- f << stringf(";\n");
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+ if (!do_inline)
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+ {
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+ f << stringf(";\n");
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+ }
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+ else
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+ {
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+ f << stringf(")");
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+ }
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return true;
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}
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@@ -1243,7 +1369,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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{
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if (cell->type[0] == '$' && !noexpr) {
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- if (dump_cell_expr(f, indent, cell))
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+ if (dump_cell_expr(f, indent, cell, false))
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return;
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}
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@@ -1400,25 +1526,42 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
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void case_body_find_regs(RTLIL::CaseRule *cs)
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{
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for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
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- for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
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- case_body_find_regs(*it2);
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+ {
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+ for (auto &c : (*it)->signal.chunks())
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+ if (c.wire != NULL && c.offset == 0 && c.width == c.wire->width)
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+ proc_consumed_wires[c.wire]++;
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+ for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
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+ case_body_find_regs(*it2);
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+ }
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- for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
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+ for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it)
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+ {
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for (auto &c : it->first.chunks())
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+ {
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if (c.wire != NULL)
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reg_wires.insert(c.wire->name);
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+ for (auto &c : it->second.chunks())
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+ if (c.wire != NULL && c.offset == 0 && c.width == c.wire->width)
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+ proc_consumed_wires[c.wire]++;
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+ }
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}
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}
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-void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, bool find_regs = false)
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+void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, bool sweep = false)
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{
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- if (find_regs) {
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+ if (sweep) {
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case_body_find_regs(&proc->root_case);
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for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
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- for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) {
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- for (auto &c : it2->first.chunks())
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- if (c.wire != NULL)
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- reg_wires.insert(c.wire->name);
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+ {
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+ for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++)
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+ {
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+ for (auto &c : it2->first.chunks())
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+ if (c.wire != NULL)
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+ reg_wires.insert(c.wire->name);
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+ for (auto &c : it2->second.chunks())
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+ if (c.wire != NULL && c.offset == 0 && c.width == c.wire->width)
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+ proc_consumed_wires[c.wire]++;
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+ }
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}
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return;
|
||||
}
|
||||
@@ -1487,9 +1630,11 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
|
||||
void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
|
||||
{
|
||||
reg_wires.clear();
|
||||
+ proc_consumed_wires.clear();
|
||||
reset_auto_counter(module);
|
||||
active_module = module;
|
||||
active_sigmap.set(module);
|
||||
+ active_modindex = ModIndex(module);
|
||||
active_initdata.clear();
|
||||
|
||||
for (auto wire : module->wires())
|
||||
@@ -1575,6 +1720,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
|
||||
|
||||
f << stringf("%s" "endmodule\n", indent.c_str());
|
||||
active_module = NULL;
|
||||
+ active_modindex = ModIndex();
|
||||
active_sigmap.clear();
|
||||
active_initdata.clear();
|
||||
}
|
||||
@@ -1605,7 +1751,12 @@ struct VerilogBackend : public Backend {
|
||||
log("\n");
|
||||
log(" -noexpr\n");
|
||||
log(" without this option all internal cells are converted to Verilog\n");
|
||||
- log(" expressions.\n");
|
||||
+ log(" expressions. implies -noinline.\n");
|
||||
+ log("\n");
|
||||
+ log(" -noinline\n");
|
||||
+ log(" without this option all internal cells driving a wire connected to\n");
|
||||
+ log(" a single internal cell are inlined into that cell and the wire is\n");
|
||||
+ log(" omitted.\n");
|
||||
log("\n");
|
||||
log(" -siminit\n");
|
||||
log(" add initial statements with hierarchical refs to initialize FFs when\n");
|
||||
@@ -1662,6 +1813,7 @@ struct VerilogBackend : public Backend {
|
||||
noattr = false;
|
||||
attr2comment = false;
|
||||
noexpr = false;
|
||||
+ noinline = false;
|
||||
nodec = false;
|
||||
nohex = false;
|
||||
nostr = false;
|
||||
@@ -1723,7 +1875,11 @@ struct VerilogBackend : public Backend {
|
||||
continue;
|
||||
}
|
||||
if (arg == "-noexpr") {
|
||||
- noexpr = true;
|
||||
+ noexpr = noinline = true;
|
||||
+ continue;
|
||||
+ }
|
||||
+ if (arg == "-noinline") {
|
||||
+ noinline = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-nodec") {
|
||||
diff --git a/kernel/modtools.h b/kernel/modtools.h
|
||||
index 409562eb..b198709d 100644
|
||||
--- a/kernel/modtools.h
|
||||
+++ b/kernel/modtools.h
|
||||
@@ -226,6 +226,10 @@ struct ModIndex : public RTLIL::Monitor
|
||||
auto_reload_module = true;
|
||||
}
|
||||
|
||||
+ ModIndex() : module(NULL)
|
||||
+ {
|
||||
+ }
|
||||
+
|
||||
ModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)
|
||||
{
|
||||
auto_reload_counter = 0;
|
||||
@@ -235,7 +239,8 @@ struct ModIndex : public RTLIL::Monitor
|
||||
|
||||
~ModIndex()
|
||||
{
|
||||
- module->monitors.erase(this);
|
||||
+ if (module)
|
||||
+ module->monitors.erase(this);
|
||||
}
|
||||
|
||||
SigBitInfo *query(RTLIL::SigBit bit)
|
||||
Loading…
Reference in New Issue
Block a user