add UART example
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{ pkgs ? import <nixpkgs> {}
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, hx ? import ../default.nix { inherit pkgs; }}:
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let
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vivadoInput = pkgs.runCommand "test-vivado-input" {
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buildInputs = [ (pkgs.python3.withPackages(ps: [hx.nmigen hx.heavycomps])) hx.yosys ];
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}
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''
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mkdir $out
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python ${./demo.py} > $out/top.v
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cat > $out/top.xdc << EOF
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set_property LOC K24 [get_ports serial_tx]
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set_property IOSTANDARD LVCMOS25 [get_ports serial_tx]
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set_property LOC K28 [get_ports clk156_p]
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set_property IOSTANDARD LVDS_25 [get_ports clk156_p]
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set_property DIFF_TERM TRUE [get_ports clk156_p]
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set_property LOC K29 [get_ports clk156_n]
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set_property IOSTANDARD LVDS_25 [get_ports clk156_n]
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set_property DIFF_TERM TRUE [get_ports clk156_n]
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create_clock -name clk156 -period 6.4 [get_nets clk156_p]
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EOF
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cat > $out/top.tcl << EOF
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create_project -force -name top -part xc7k325t-ffg900-2
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set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
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add_files {top.v}
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set_property library work [get_files {top.v}]
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read_xdc top.xdc
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synth_design -top top -part xc7k325t-ffg900-2
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opt_design
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place_design
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route_design
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
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write_bitstream -force top.bit
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quit
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EOF
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'';
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in
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hx.vivado.buildBitstream {
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name = "test-design";
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src = vivadoInput;
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}
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@ -0,0 +1,41 @@
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from nmigen import *
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from nmigen.back import verilog
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from heavycomps import uart
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class Top:
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def __init__(self, clk_freq=156e6, baudrate=115200):
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self.clk_freq = clk_freq
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self.baudrate = baudrate
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self.clk156_p = Signal()
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self.clk156_n = Signal()
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self.serial_tx = Signal()
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def elaborate(self, platform):
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m = Module()
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cd_sync = ClockDomain(reset_less=True)
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m.domains += cd_sync
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m.submodules.clock = Instance("IBUFGDS",
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i_I=self.clk156_p, i_IB=self.clk156_n, o_O=cd_sync.clk)
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tx = uart.RS232TX(round(2**32*self.baudrate/self.clk_freq))
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m.submodules.tx = tx
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m.d.comb += [
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tx.stb.eq(1),
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tx.data.eq(ord("A")),
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self.serial_tx.eq(tx.tx)
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]
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return m
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def main():
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top = Top()
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output = verilog.convert(Fragment.get(top, None),
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ports=(top.clk156_p, top.clk156_n, top.serial_tx))
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print(output)
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if __name__ == "__main__":
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main()
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