add simple test for UART
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472114c136
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@ -0,0 +1,41 @@
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import unittest
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from nmigen import *
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from nmigen.back.pysim import *
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from heavycomps import uart
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class Loopback:
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def __init__(self, tuning_word=2**31):
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self.tx = uart.RS232TX(tuning_word)
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self.rx = uart.RS232RX(tuning_word)
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def elaborate(self, platform):
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m = Module()
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m.submodules.tx = self.tx
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m.submodules.rx = self.rx
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m.d.comb += self.rx.rx.eq(self.tx.tx)
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return m
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class TestUART(unittest.TestCase):
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def test_loopback(self):
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dut = Loopback()
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test_vector = [32, 129, 201, 39, 0, 255]
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with Simulator(Fragment.get(dut, None)) as sim:
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sim.add_clock(1e-6)
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def send():
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for value in test_vector:
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yield from dut.tx.write(value)
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def receive():
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for value in test_vector:
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received = yield from dut.rx.read()
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self.assertEqual(received, value)
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sim.add_sync_process(send)
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sim.add_sync_process(receive)
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sim.run()
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@ -1,6 +1,5 @@
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from nmigen import *
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from nmigen.lib.cdc import MultiReg
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from nmigen.cli import main
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class RS232RX:
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@ -50,6 +49,14 @@ class RS232RX:
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return m
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def read(self):
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while not (yield self.stb):
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yield
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value = yield self.data
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# clear stb, otherwise multiple calls to this generator keep returning the same value
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yield
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return value
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class RS232TX:
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def __init__(self, tuning_word):
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@ -92,19 +99,10 @@ class RS232TX:
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return m
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class Loopback:
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def elaborate(self, platform):
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m = Module()
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tuning_word = 2**31
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tx = RS232TX(tuning_word)
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rx = RS232RX(tuning_word)
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m.submodules += tx, rx
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m.d.comb += rx.rx.eq(tx.tx)
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m.d.comb += tx.data.eq(42)
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m.d.comb += tx.stb.eq(1)
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return m
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if __name__ == "__main__":
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uart = Loopback()
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main(uart)
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def write(self, data):
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yield self.stb.eq(1)
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yield self.data.eq(data)
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yield
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while not (yield self.ack):
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yield
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yield self.stb.eq(0)
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